THS4226EVM User’s Guide May 2003 High Performance Linear Products SLOU157
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
EVM WARNINGS AND RESTRICTIONS It is important to operate this EVM within the input voltage range of 4 V (differential) and 7.5 V (Vs–, Vs+) when using a dual-supply power source—maximum 15 V when using a single-supply power source (Vs). Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Information About Cautions and Warnings Preface Read This First Information About Cautions and Warnings This book may contain cautions and warnings. This is an example of a caution statement. A caution statement describes a situation that could potentially damage your software or equipment. This is an example of a warning statement. A warning statement describes a situation that could potentially cause harm to you. The information in a caution or a warning is provided for your protection.
Trademarks This EVM contains components that can potentially be damaged by electrostatic discharge. Always transport and store the EVM in its supplied ESD bag when not in use. Handle using an antistatic wristband. Operate on an antistatic work surface. For more information on proper handling, refer to SSYA008. Related Documentation From Texas Instruments The URL’s below are correct as of the date of publication of this manual. Texas Instruments applications apologizes if they change over time.
Contents Contents 1 Introduction and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 Evaluation Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 2 Using the THS4226EVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 3 THS4226EVM Applications . . . . . . . . . . . . . . . . . . . .
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Chapter 1 Introduction and Description This EVM provides a platform for testing the THS4226 in the 10-pin MSOP (DGQ) package. It contains the high-speed op amp, a number of passive components, and various features and footprints that enable the user to experiment, test, and verify various operational amplifier circuit implementations. 1.1 Evaluation Schematic As delivered, the EVM has a fully functional example circuit—just add power supplies, a signal source, and monitoring instrument.
Evaluation Schematic - Power PADt heatsinking capability EVM Channel 1: The default configuration design for EVM channel 1 provides a voltage gain of +2. This voltage gain is the ratio of the voltage at the output pin of the amplifier (pin 1) to the voltage at the J3 input. R1 and R6 are equal and therefore provide for a gain of +2. The noninverting gain of the EVM channel 1 amplifier, when using the default configuration, is affected by a voltage divider composed of R5 and R4.
Evaluation Schematic Figure 1–1. Schematic of the THS4226EVM J9 J7 FB2 GND FB1 J8 –VS(IN) C5 22 µF + + +VS(IN) TP1 TP2 –VS +VS C6 22 µF R6 PD1 PD2 1.3 kΩ PD1 +VS PD2 C2* C1* C4 100 pF J2 V1in– U1A THS4226 1 10 1.3 kΩ 3 R2 52.3 Ω R5 5 4 R3 49.9 Ω J1 V1out 49.9 Ω + 2 – R1 C8 0.1 µF PD1 C3 100 pF J3 C7 0.1 µF R4 453 Ω V1in+ –VS R7 0 J4 V2in– 7 R11 9 J6 V2out 49.9 Ω 6 R9* J5 V2in+ U1B + 8 – R8* PD2 R10 49.
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Chapter 2 Using the THS4226EVM This chapter shows how to connect the THS4226EVM to test equipment. It is recommended that the user connect the EVM as shown in this chapter to avoid damage to the EVM or the THS4226 installed on the board. Figure 2- 1 shows how to connect the power supplies, 50-Ω signal source and 50-Ω monitoring instrument. Figure 2 - 1.
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Chapter 3 THS4226EVM Applications Example applications are presented in this chapter. These applications demonstrate the most popular circuits to the user, but many other circuits can be constructed. The user is encouraged to experiment with different circuits, exploring new and creative design techniques. That is the function of an evaluation board. 3.1 Inverting Video Gain Stage The circuit described in Chapter 1 is an inverting gain stage with a voltage divider on the output.
Noninverting Video Gain Stage 3.2 Noninverting Video Gain Stage For a noninverting stage in EVM channel 2, the gain error imposed by R9 can be eliminated by replacing R9 with a 0-Ω resistor. Rt is the termination resistor of 75 Ω, as shown in Figure 3–2. As in the inverting gain stage example above, R12 has been removed. The following equation indicates the voltage gain from J5 to J6 when connected to a 75-Ω measurement instrument. ǒ V Ǔ ǒRt )RtR11Ǔ + 1 O + 1 ) R7 R8 V I (2) Figure 3–2.
Power-Down Functionality Saves Power 3.4 Power-Down Functionality Saves Power The THS4226 EVM features a power-down pin (PD) for each channel, which lowers the quiescent current from 14 mA/channel down to 700 µA/channel, ideal for reducing system power. The power-down pin of the amplifier defaults to the positive supply voltage in the absence of an applied voltage, putting the amplifier in the power-on mode of operation.
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Chapter 4 EVM Hardware Description This chapter describes the EVM hardware. It includes the EVM parts list, and printed circuit board layout. Table 4–1. THS4226EVM Bill of Materials Item Description SMD Size Reference Designator 1 Bead, ferrite, 3A, 80 Ω 1206 FB1, FB2 2 Cap, 22 µF, tanatalum, 25 V, 10% D 3 Cap, 0.
Figure 4 - 1. Top View Showing Top Layer and Component Placement for THS4226EVM Figure 4 - 2.
Figure 4 - 3. Internal Plane (Layer 3) Power Plane7 Figure 4 - 4.
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