Datasheet

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100 k 1 M 10 M 100 M 1 G
f - Frequency - Hz
Powerdown Output Impedance - Ω
Gain = 2
R
F
= 1 kΩ
V
S
= ±15 V and ±5 V
THS3110
THS3111
SLOS422E –SEPTEMBER 2003–REVISED OCTOBER 2009........................................................................................................................................ www.ti.com
Figure 62 shows the total system output impedance POWER-DOWN REFERENCE PIN
which includes the amplifier output impedance in OPERATION
parallel with the feedback plus gain resistors, which
In addition to the power-down pin, the THS3110
cumulate to 1870 Ω. Figure 51 shows this circuit
features a reference pin (REF) which allows the user
configuration for reference.
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The tables below show examples and illustrate
the relationship between the reference voltage and
the power-down thresholds. In the table, the threshold
levels are derived by the following equations:
PD ≤ REF + 0.8 V for enable
PD ≥ REF + 2.0 V for disable
where the usable range at the REF pin is
V
S–
≤ V
REF
≤ (V
S+
– 4 V).
The recommended mode of operation is to tie the
REF pin to midrail, thus setting the enable/disable
Figure 62. Power-Down Output Impedance vs
thresholds to V
midrail
+ 0.8 V and V
midrail
+ 2 V
Frequency
respectively.
As with most current feedback amplifiers, the internal
POWER-DOWN THRESHOLD VOLTAGE LEVELS
architecture places some limitations on the system
SUPPLY REFERENCE PIN ENABLE DISABLE
when in power-down mode. Most notably is the fact
VOLTAGE (V) VOLTAGE (V) LEVEL (V) LEVEL (V)
that the amplifier actually turns ON if there is a ±0.7 V
±15, ±5 0.0 0.8 2.0
or greater difference between the two input nodes
±15 2.0 2.8 4
(V+ and V–) of the amplifier. If this difference
±15 –2.0 –1.2 0
exceeds ±0.7 V, the output of the amplifier creates an
±5 1.0 1.8 3
output voltage equal to approximately [(V+ – V–) –
0.7 V] × Gain. Also, if a voltage is applied to the
±5 –1.0 –0.2 1
output while in power-down mode, the V– node
+30 15 15.8 17
voltage is equal to V
O(applied)
× R
G
/(R
F
+ R
G
). For low
+10 5.0 5.8 7
gain configurations and a large applied voltage at the
output, the amplifier may actually turn ON due to the
Note that if the REF pin is left unterminated, it floats
aforementioned behavior.
to the positive rail and falls outside of the
recommended operating range given above (V
S–
≤
The time delays associated with turning the device on
V
REF
≤ V
S+
– 4 V). As a result, it no longer serves as
and off are specified as the time it takes for the
a reliable reference for the PD pin and the
amplifier to reach either 10% or 90% of the final
enable/disable thresholds given above no longer
output voltage. The time delays are in the order of
apply. If the PD pin is also left unterminated, it also
microseconds because the amplifier moves in and out
floats to the positive rail and the device is disabled. If
of the linear mode of operation in these transitions.
balanced, split supplies are used (±V
S
) and the REF
and PD pins are grounded, the device is enabled.
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