Datasheet

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DIE
Side View (a)
DIE
End View (b)
Thermal
Pad
Bottom View (c)
PowerPAD ™ DESIGN CONSIDERATIONS
0.140
0.060
0.060
0.010
vias
Top View
0.035
0.080
0.050
0.176
0.030
0.026
0.010
0.035
0.100
0.300
Pin 1
THS3092
THS3096
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
• Connections to other wideband devices on the leadframe upon which the die is mounted [see
board may be made with short direct traces or Figure 66 (a) and Figure 66 (b)]. This arrangement
through onboard transmission lines. For short results in the lead frame being exposed as a thermal
connections, consider the trace and the input to pad on the underside of the package [see
the next device as a lumped capacitive load. Figure 66 (c)]. Because this thermal pad has direct
Relatively wide traces (50 mils to 100 mils) thermal contact with the die, excellent thermal
should be used, preferably with ground and performance can be achieved by providing a good
power planes opened up around them. Estimate thermal path away from the thermal pad. Note that
the total capacitive load and determine if isolation devices such as the THS3092/6 have no electrical
resistors on the outputs are necessary. Low connection between the PowerPAD and the die.
parasitic capacitive loads (< 4 pF) may not need
The PowerPAD package allows for both assembly
an R
S
since the THS3092/6 are nominally
and thermal management in one manufacturing
compensated to operate with a 2-pF parasitic
operation. During the surface-mount solder operation
load. Higher parasitic capacitive loads without an
(when the leads are being soldered), the thermal pad
RS are allowed as the signal gain increases
can also be soldered to a copper area underneath the
(increasing the unloaded phase margin). If a long
package. Through the use of thermal paths within this
trace is required, and the 6-dB signal loss
copper area, heat can be conducted away from the
intrinsic to a doubly-terminated transmission line
package into either a ground plane or other heat
is acceptable, implement a matched impedance
dissipating device.
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
The PowerPAD package represents a breakthrough
microstrip and stripline layout techniques). A
in combining the small area and ease of assembly of
50- Ω environment is not necessary onboard, and
surface mount with the, heretofore, awkward
in fact, a higher impedance environment
mechanical methods of heatsinking.
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3092/6 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
Figure 66. Views of Thermal Enhanced Package
impedance of the destination device: this total
effective impedance should be set to match the
Although there are many ways to properly heatsink
trace impedance. If the 6-dB attenuation of a
the PowerPAD package, the following steps illustrate
doubly terminated transmission line is
the recommended approach.
unacceptable, a long trace can be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
• Socketing a high speed part like the THS3092/6
are not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost
impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3092/6 parts directly onto the board.
The THS3092/6 are available in a
Figure 67. DDA PowerPAD PCB Etch and Via
thermally-enhanced PowerPAD family of packages.
Pattern
These packages are constructed using a downset
22
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