Datasheet

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PRINTED-CIRCUIT BOARD LAYOUT
POWER-DOWN REFERENCE PIN
THS3092
THS3096
SLOS428B – DECEMBER 2003 – REVISED FEBRUARY 2006
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final TECHNIQUES FOR OPTIMAL
output voltage. The time delays are in the order of PERFORMANCE
microseconds because the amplifier moves in and out
Achieving optimum performance with high frequency
of the linear mode of operation in these transitions.
amplifier, like the THS3092/6, requires careful
attention to board layout parasitic and external
component types.
OPERATION
Recommendations that optimize performance include:
In addition to the power-down pin, the THS3096
• Minimize parasitic capacitance to any ac ground
features a reference pin (REF) which allows the user
for all of the signal I/O pins. Parasitic capacitance
to control the enable or disable power-down voltage
on the output and input pins can cause instability.
levels applied to the PD pin. In most split-supply
To reduce unwanted capacitance, a window
applications, the reference pin is connected to
around the signal I/O pins should be opened in all
ground. In either case, the user needs to be aware of
of the ground and power planes around those
voltage-level thresholds that apply to the power-down
pins. Otherwise, ground and power planes should
pin. The tables below show examples and illustrate
be unbroken elsewhere on the board.
the relationship between the reference voltage and
• Minimize the distance (< 0.25”) from the power
the power-down thresholds. In the table, the threshold
supply pins to high frequency 0.1- µF and 100-pF
levels are derived by the following equations:
decoupling capacitors. At the device pins, the
PD ≤ REF + 0.8 V for disable
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
PD ≥ REF + 2.0 V for enable
narrow power and ground traces to minimize
where the usable range at the REF pin is V
S–
≤ V
REF
≤
inductance between the pins and the decoupling
(V
S+
– 4 V).
capacitors. The power supply connections should
always be decoupled with these capacitors.
The recommended mode of operation is to tie the
Larger (6.8 µF or more) tantalum decoupling
REF pin to midrail, thus setting the enable/disable
capacitors, effective at lower frequency, should
thresholds to V
midrail
+ 2 V and V
midrail
+ 0.8 V
also be used on the main supply pins. These may
respectively.
be placed somewhat farther from the device and
may be shared among several devices in the
Table 2. Power-Down Threshold Voltage Levels
same area of the PC board.
SUPPLY REFERENCE ENABLE DISABLE
• Careful selection and placement of external
VOLTAGE PIN VOLTAGE LEVEL LEVEL
components preserve the high frequency
(V) (V) (V) (V)
performance of the THS3092/6. Resistors should
±15, ±5 0.0 2.0 0.8
be a very low reactance type. Surface-mount
±15 2.0 4.0 2.8
resistors work best and allow a tighter overall
±15 –2.0 0.0 –1.2
layout. Again, keep their leads and PC board
±5 1.0 3.0 1.8
trace length as short as possible. Never use
wirebound type resistors in a high frequency
±5 –1.0 1.0 –0.2
application. Since the output pin and inverting
30 15 17 15.8
input pins are the most sensitive to parasitic
10 5.0 7.0 5.8
capacitance, always position the feedback and
series output resistors, if any, as close as
Note that if the REF pin is left unterminated, it will
possible to the inverting input pins and output
float to the positive rail and will fall outside of the
pins. Other network components, such as input
recommended operating range given above V
S–
≤
termination resistors, should be placed close to
V
REF
≤ (V
S+
– 4 V). As a result, it will no longer serve
the gain-setting resistors. Even with a low
as a reliable reference for the PD pin, and the
parasitic capacitance shunting the external
enable/disable thresholds given above will no longer
resistors, excessively high resistor values can
apply. If the PD pin is also left unterminated, it will
create significant time constants that can degrade
also float to the positive rail and the device will be
performance. Good axial metal-film or
enabled. If balanced, split supplies are used (±V
S
)
surface-mount resistors have approximately 0.2
and the REF and PD pins are grounded, the device
pF in shunt with the resistor. For resistor values >
will be disabled.
2.0 k Ω, this parasitic capacitance can add a pole
and/or a zero that can effect circuit operation.
Keep resistor values as low as possible,
consistent with load driving considerations.
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