Datasheet

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SLAS248D − DECEMBER 1999 − REVISED SEPTEMBER 2005
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PRINCIPLES OF OPERATION
Table 4. Control Register, Address 3, Read
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES
Table 5. Control Register, Address 3, Write
BIT D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function PWD REF FOR TM2 TM1 TM0 OFF RES RES RES RES RES RES RES
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PWD: Power down 0 = normal operation 1 = power down
REF: Reference select 0 = internal reference 1 = external reference
FOR: Output format 0 = straight binary 1 = 2s complement
TM2−0: Test mode 000 = normal operation
001 = both inputs = REF−
010 = IN+ at V
CM
(Voltage at CML pin), IN− at REF−
011 = IN+ at REF+, IN− at REF−
100 = normal operation
101 = both inputs = REF+
110 = IN+ at REF−, IN− at V
CM
(Voltage at CML pin)
111 = IN+ at REF−, IN− at REF+
OF: Offset correction 0 = enable 1 = disable
RES Reserved Must be set to 0.
APPLICATION INFORMATION
driving the analog input
The THS1401/3/8 ADCs have a fully differential input. A differential input is advantageous with respect to SNR,
SFDR, and THD performance because the signal peak-to-peak level is 50% of a comparable single-ended
input.
There are three basic input configurations:
D Fully differential
D Transformer coupled single-ended to differential
D Single-ended
fully differential configuration
In this configuration, the ADC converts the difference (IN) of the two input signals on IN+ and IN−.
100 pF
IN+
IN−
THS1401/3/8
22
100 pF
22
Figure 19. Differential Input