Datasheet

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
32
INTERFACING THE THS1206 TO THE TMS320C54X USING I/O STROBE
The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write timings (using
R/W
, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/W
DATA_AV
CONV_CLK
DATA
RD
DV
DD
THS1206 TMS320C54x
I/O STRB
A15
R/W
INTX
BCLK
DATA
Read Timing (using RD, RD-controlled)
Figure 38 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts
as the read-input in this configuration. This timing is called RD
-controlled because RD is the last external signal of CS0,
CS1, and RD,
which becomes valid.
90%90%
90%
10%
t
w(RD
)
t
su(CS)
t
h(CS)
t
a
t
h
t
d(CSDAV)
CS0
CS1
WR
RD
D(0–11)
DATA_AV
10%
Figure 38. Read Timing Diagram Using RD (RD-controlled)
Read Timing Parameter (RD
-controlled)
PARAMETER MIN TYP MAX UNIT
t
su(CS)
Setup time, RD low to last CS valid 0 ns
t
a
Access time, last CS valid to data valid 0 10 ns
t
d(CSDAV)
Delay time, last CS valid to DATA_AV inactive 12 ns
t
h
Hold time, first CS invalid to data invalid 0 5 ns
t
h(CS)
Hold time, RD change to first CS invalid 5 ns
t
w(RD
)
Pulse duration, RD active 10 ns