Datasheet

THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
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31
Write Timing (using R/W, CS0-controlled)
Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD
input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0
, CS1, and R/W, which becomes valid.
90%
90%
90%
10%
t
w(CS)
t
su(R/W
)
t
h(R/W
)
CS0
CS1
WR
RD
D(0–11)
DATA_AV
10%
t
su
t
h
Figure 37. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (RD
-controlled)
PARAMETER MIN TYP MAX UNIT
t
su(R/W
)
Setup time, R/W stable to last CS valid 0 ns
t
su
Setup time, data valid to first CS invalid 5 ns
t
h
Hold time, first CS invalid to data invalid 2 ns
t
h(R/W
)
Hold time, first CS invalid to R/W change 5 ns
t
w(CS)
Pulse duration, CS active 10 ns
INTERFACING THE THS1206 TO THE TMS320C30/31/33 DSP
The following application circuit shows an interface of the THS1206 to the TMS320C30/31/33 DSPs. The read and write
timings (using R/W
, CS0-controlled) shown before are valid for this specific interface.
CS0
CS1
R/
W
DATA_AV
CONV_CLK
DATA
RD
DV
DD
THS1206
TMS320C30/31/33
STRB
A23
R/W
INTX
TOUT
DATA