Datasheet
THS1206
SLAS217H – MAY 1999 – REVISED JULY 2003#
www.ti.com
18
CONTINUOUS CONVERSION MODE
The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In
continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal
CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
Figure 25 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum
throughput rate is 6 MSPS in this mode. The timing of the DATA_AV signal is shown here in the case of a trigger level set
to 1 or 4.
Sample N
Channel 1
Sample N+1
Channel 1
Sample N+2
Channel 1
Sample N+3
Channel 1
Sample N+4
Channel 1
Sample N+5
Channel 1
Sample N+6
Channel 1
Sample N+7
Channel 1
Sample N+8
Channel 1
Data N–5
Channel 1
Data N–4
Channel 1
Data N–3
Channel 1
Data N–2
Channel 1
Data N–1
Channel 1
Data N
Channel 1
Data N+1
Channel 1
Data N+2
Channel 1
Data N+3
Channel 1
t
d(A)
t
w(CONV_CLKH)
t
w(CONV_CLKL)
t
c
t
d(O)
t
d(DATA_AV)
t
d(DATA_AV)
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 1
DATA_AV,
Trigger Level = 4
t
d(pipe)
50% 50%
Figure 25. Timing of Continuous Conversion Mode (1-channel operation)
Figure 26 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum
throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted
data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 2 or 4.
AIN
CONV_CLK
Data Into
FIFO
DATA_AV,
Trigger Level = 2
DATA_AV,
Trigger Level = 4
Data N–3
Channel 2
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
Data N+1
Channel 2
t
d(DATA_AV)
t
w(CONV_CLKH)
t
w(CONV_CLKL)
t
d(A)
Sample N
Channel 1,2
Sample N+1
Channel 1,2
Sample N+2
Channel 1,2
Sample N+3
Channel 1,2
Sample N+4
Channel 1,2
t
c
t
d(O)
t
d(Pipe)
t
d(DATA_AV)
50% 50%
Figure 26. Timing of Continuous Conversion Mode (2-channel operation)