Information

TFP410
TI PanelBus DIGITAL TRANSMITTER
SLDS145B OCTOBER 2001 REVISED MAY 2011
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc specifications
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
V
High level input voltage (CMOS input)
V
REF
= DV
DD
0.7 V
DD
V
V
IH
High-level input voltage (CMOS input)
0.5 V V
REF
0.95 V V
REF
+ 0.2
V
V
Low level input voltage (CMOS input)
V
REF
= DV
DD
0.3V
DD
V
V
IL
Low-level input voltage (CMOS input)
0.5 V V
REF
0.95 V V
REF
0.2
V
V
OH
High-level digital output voltage (open-drain output) V
DD
= 3 V, I
OH
= 20 μA 2.4 V
V
OL
Low-level digital output voltage (open-drain output) V
DD
= 3.6 V, I
OL
= 4 mA 0.4 V
I
IH
High-level input current V
I
= 3.6 V ±25 μA
I
IL
Low-level input current V
I
= 0 ±25 μA
V
H
DVI single-ended high-level output voltage AV
DD
0.01 AV
DD
+ 0.01 V
V
L
DVI single-ended low-level output voltage
AV
DD
= 3.3 V ± 5%,
R
50 Ω ± 10%
AV
DD
0.6 AV
DD
0.4 V
V
SWING
DVI single-ended output swing voltage
R
T
= 50 Ω ± 10%,
R
TFADJ
=
5
1
0
Ω ± 1
%
400 600 mV
P-P
V
OFF
DVI single-ended standby/off output voltage
R
TFADJ
=
510 Ω ± 1%
AV
DD
0.01 AV
DD
+ 0.01 V
I
PD
Power-down current (see Note 3) 200 500 μA
I
IDD
Normal power supply current Worst case pattern
200 250 mA
R
T
is the single-ended termination resistance at the receiver end of the DVI link.
Black and white checkerboard pattern, each checker is one pixel wide.
NOTE 3: Assumes all inputs to the transmitter are not toggling.
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(IDCK)
IDCK frequency 25 165 MHz
t
(pixel)
Pixel time period (see Note 4) 6.06 40 ns
t
(IDCK)
IDCK duty cycle 30% 70%
t
(ijit)
IDCK clock jitter tolerance 2 ns
t
r
DVI output rise time (20-80%) (see Note5) 75 240 ps
t
f
DVI output fall time (20-80%) (see Note 5) 75 240 ps
t
sk(D)
DVI output intra-pair + to differential skew (see Note 6)
f
IDCK
= 165 MHz
50 ps
t
sk(CC)
DVI output inter-pair or channel-to-channel skew (see Note 6)
1.2 ns
t
ojit
DVI output clock jitter, max. (see Note 7) 150 ps
t
su(IDF)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge
Single edge
1.2 ns
t
h(IDF)
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge
(BSEL=1, DSEL=0,
DKEN=0, EDGE=0)
1.3 ns
t
su(IDR)
Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge
Single edge
1.2 ns
t
h(IDR)
Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge
(BSEL=1, DSEL=0,
DKEN=0, EDGE=1)
1.3 ns
t
su(ID)
Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising
edge
Dual edge
(BSEL=0, DSEL=1,
DKEN=0)
0.9 ns
t
h(ID)
Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising
edge
Dual edge (BSEL=0,
DSEL=1, DKEN=0)
1 ns
t
(STEP)
De-skew trim increment DKEN = 1 350 ps
NOTES: 4. t
(pixel)
is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t
(pixel)
.
5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.
6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.
7. Relative to input clock (IDCK).