Information

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
register descriptions (continued)
DE_CNT Sub-Address = 37−36 Read/Write Default = 0x0000
7
6 5 4 3 2 1 0
DE_CNT[7:0]
Reserved DE_CNT[10:8]
These read/write registers define the width of the active display, in pixels, when the DE generator is enabled.
DE_LIN Sub-Address = 39−38 Read/Write Default = 0x0000
7 6 5 4 3 2 1 0
DE_LIN[7:0]
Reserved DE_LIN[10:8]
These read/write registers define the height of the active display, in lines, when the DE generator is enabled.
H_RES Sub-Address = 3B−3A Read Only
7
6 5 4 3 2 1 0
H_RES[7:0]
Reserved H_RES[10:8]
These read-only registers return the number of pixels between consecutive HSYNC pulses.
V_RES Sub-Address = 3D−3C Read Only
7 6 5 4 3 2 1 0
V_RES[7:0]
Reserved V_RES[10:8]
These read-only registers return the number of lines between consecutive VSYNC pulses.
I
2
C interface
The I
2
C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCL
clock line and the SDA serial data line. The basic I
2
C access cycles are shown in Figure 10 and Figure 11.
Start Condition (S) Stop Condition (P)
SDA
SCL
Figure 10. I
2
C Start and Stop Conditions
The basic access write cycle consists of the following:
1. A start condition
2. A slave address cycle
3. A sub-address cycle
4. Any number of data cycles
5. A stop condition