Information

TFP410
TI PanelBus™ DIGITAL TRANSMITTER
SLDS145B − OCTOBER 2001 − REVISED MAY 2011
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
T.M.D.S. pixel data and control signal encoding
For transition minimized differential signaling (T.M.D.S.), only one of two possible T.M.D.S. characters for a
given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros
previously sent and transmits the character that minimizes the number of transitions and approximates a dc
balance of the transmission line. Three T.M.D.S. channels are used to transmit RGB pixel data during the active
video interval (DE = High). These same three channels are also used to transmit HSYNC, VSYNC, and three
user definable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low). The
following table maps the transmitted output data to the appropriate T.M.D.S. output channel in a DVI-compliant
system.
INPUT PINS
(VALID FOR DE = High)
T.M.D.S. OUTPUT CHANNEL
TRANSMITTED PIXEL DATA
ACTIVE DISPLAY (DE = High)
DATA[23:16] Channel 2 (TX2 ±) Red[7:0]
DATA[15:8] Channel 1 (TX1 ±) Green[7:0]
DATA[7:0] Channel 0 (TX0 ±) Blue[7:0]
INPUT PINS
(VALID FOR DE = Low)
T.M.D.S. OUTPUT CHANNEL
TRANSMITTED CONTROL DATA
BLANKING INTERVAL (DE = Low)
CTL3, CTL2 (see Note 8) Channel 2 (TX2 ±) CTL[3:2]
CTL1 (See Note 8) Channel 1 (TX1 ±) CTL[1]
HSYNC, VSYNC Channel 0 (TX0 ±) HSYNC, VSYNC
NOTE 8: The TFP410 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The CTL3 input is reserved for HDCP
compliant DVI TXs and the CTL[2:1] inputs are reserved for future use. When DE = high, CTL and SYNC pins must be held
constant.
universal graphics controller interface voltage signal levels
The universal graphics controller interface can operate in the following two distinct voltage modes:
D The high-swing mode where standard 3.3-V CMOS signaling levels are used.
D The low-swing mode where adjustable 1.1-V to 1.8-V signaling levels are used.
To select the high-swing mode, the V
REF
input pin must be tied to the 3.3-V power supply.
To select the low-swing mode, the V
REF
must be 0.55 to 0.95 V.
In the low-swing mode, V
REF
is used to set the midpoint of the adjustable signaling levels. The allowable range
of values for V
REF
is from 0.55 V to 0.9 V. The typical approach is to provide this from off chip by using a simple
voltage-divider circuit. The minimum allowable input signal swing in the low-swing mode is V
REF
±0.2 V. In
low-swing mode, the V
REF
input is common to all differential input receivers.
universal graphics controller interface clock inputs
The universal graphics controller interface of the TFP410 supports both fully differential and single-ended clock
input modes. In the differential clock input mode, the universal graphics controller interface uses the crossover
point between the IDCK+ and IDCK− signals as the timing reference for latching incoming data (DATA[23:0],
DE, HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The
differential clock input mode is only available in the low-swing mode. In the single-ended clock input mode, the
IDCK+ input (Pin 57) should be connected to the single-ended clock source and the IDCK− input (Pin 56) should
be tied to GND.
The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit
single-edge, input clocking modes. In the 12-bit dual-edge , the 12-bit data is latched on each edge of the input
clock. In the 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when
EDGE = 1 and the falling edge of the input clock when EDGE = 0.
DKEN and DK[3:1] allow the user to compensate the skew between IDCK± and the pixel data and control
signals. See the description of the CTL_3_MODE register for details.