Datasheet

3
CTL[3:1]
2 1
3
CTL[2:1]
RSVD
2 1
www.ti.com Input Voltage Clarifications
Sheet 10, in note 8, change the second sentence
From: The CTL3 input is reserved for HDCP compliant DVI TXs and the CTL[2:1] inputs are reserved
for future use.
To: CTL3 is reserved for HDCP and is always encoded as 0. The CTL[2:1] inputs are reserved for
future use.
Sheet 19, register CTL_3_MODE, change definition of bits 3:1 in the diagram
From:
To:
In the text below the diagram, change the CTL bit definition name
From: CTL[3:1]:This read/write register contains the values of the three CTL[3:1] bits that are output
on the DVI port during the blanking interval.
To: CTL[2:1]:This read/write register contains the values of the three CTL[2:1] bits that are output
on the DVI port during the blanking interval.
Input Voltage Clarifications
In the DC specification table, V
IH
and V
IL
are not clear for signals that are not part of the video input bus.
Changes in the Document Text
Sheet 7, in the dc specifications table, change the V
IH
and V
IL
specifications to contain the following
information:
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Data, DE, VSYNC, V
REF
= DV
DD
0.7 × V
DD
HSYNC and
High-level input
V
IH
0.5 V ≤ V
REF
≤ 0.95 V V
REF
+ 0.2 V
IDCK+/–
voltage
Other inputs 0.7 × V
DD
Data, DE, VSYNC, V
REF
= DV
DD
0.3 × V
DD
HSYNC and
Low-level input
V
IL
0.5 V ≤ V
REF
≤ 0.95 V V
REF
– 0.2 V
IDCK+/–
voltage
Other inputs 0.3 × V
DD
SLLZ030A – June 2003 – Revised April 2009 Errata to TFP410 Datasheet 3
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