Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing diagrams
t
r
t
f
80% V
OD
20% V
OD
DVI
Outputs
Figure 1. Rise and Fall Time for DVI Outputs
t
h(IDF)
t
su(IDF)
t
h(IDR)
t
su(IDR)
V
IH
V
IL
IDCK+
DATA[23:0], DE,
HSYNC, VSYNC
IDCK−
Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK±
t
su(ID)
t
h(ID)
V
IH
V
IL
IDCK+
DATA[23:0], DE,
HSYNC, VSYNC
t
h(ID)
t
su(ID)
Figure 3. Dual-Edge Data Setup/Hold Times to IDCK+
t
sk(D)
50%
TX+
TX−
Figure 4. Analog Output Intra-Pair ± Differential Skew
t
sk(CC)
50%
50%
TXN
TXM
Figure 5. Analog Output Channel-to-Channel Skew