Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) − (continued)
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
(IDCK)
IDCK frequency 25 165 MHz
t
(pixel)
Pixel time period (see Note 1) 6.06 40 ns
t
(IDCK)
IDCK duty cycle 30% 70%
t
(ijit)
IDCK clock jitter tolerance 2 ns
t
DVI output rise time (20 80%) (see Note 2)
f 165 MHz
0°C to 70°C 75 240
ps
t
r
DVI output rise time (20-80%) (see Note 2) f
(IDCK)
= 165 MHz
−55°C to 125°C 45 320
ps
t
DVI output fall time (20 80%) (see Note 2)
f 165 MHz
0°C to 70°C 75 240
ps
t
f
DVI output fall time (20-80%) (see Note 2) f
(IDCK)
= 165 MHz
−55°C to 125°C 45 320
ps
t
sk(D)
DVI output intra-pair + to − differential skew
(see Note 3)
f
(IDCK)
= 165 MHz 50 ps
t
sk(CC)
DVI output inter-pair or channel-to-channel
skew (see Note 3)
f
(IDCK)
= 165 MHz 1.2 ns
t
DVI output clock jitter max (see Note 4)
f 165 MHz
0°C to 70°C 150
ps
t
ojit
DVI output clock jitter, max. (see Note 4) f
(IDCK)
= 165 MHz
−55°C to 125°C 190
ps
t
su(IDF)
Data, DE, VSYNC, HSYNC setup time to
IDCK+ falling edge
Single edge
(BSE = 1, DSEL = 0,
DKEN = 0, EDGE = 0)
IDCK = 165 MHz 1.5 ns
t
h(IDF)
Data, DE, VSYNC, HSYNC hold time to
IDCK+ falling edge
Single edge
(BSE = 1, DSEL = 0,
DKEN = 0, EDGE = 0)
IDCK = 165 MHz 1.5 ns
t
su(IDR)
Data, DE, VSYNC, HSYNC setup time to
IDCK+ rising edge
Single edge
(BSEL = 1, DSEL = 0,
DKEN = 0, EDGE = 1)
IDCK = 165 MHz 1.5 ns
t
h(IDR)
Data, DE, VSYNC, HSYNC hold time to
IDCK+ rising edge
Single edge
(BSEL = 1, DSEL = 0,
DKEN = 0, EDGE = 1)
IDCK = 165 MHz 1.5 ns
t
su(ID)
Data, DE, VSYNC, HSYNC setup time to
IDCK+ falling/rising edge
Dual edge
(BSEL = 0, DSEL = 1,
DKEN = 0)
IDCK = 165 MHz 0.9 ns
t
h(ID)
Data, DE, VSYNC, HSYNC hold time to
IDCK+ falling/rising edge
Dual edge (BSEL = 0,
DSEL = 1, DKEN = 0)
IDCK = 165 MHz 1 ns
t
(STEP)
De-skew trim increment DKEN = 1 IDCK = 165 MHz 350 ps
NOTES: 1. t
(pixel)
is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t
(pixel)
.
2. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.
3. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger
4. Relative to input clock (IDCK)