Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
dc specifications
PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT
Data, DE, VSYNC,
V
REF
= DV
DD
0.7 V
DD
V
IH
High-level input voltage
Data
,
DE
,
VSYNC
,
HSYNC, and IDCK+/−
0.5 V ≤ V
REF
≤ 0.95 V V
REF
+ 0.2
V
V
IH
High level input voltage
Other inputs 0.7 V
DD
V
L l l i t lt
Data, DE, VSYNC,
V
REF
= DV
DD
0.3 V
DD
V
IL
Low-level input voltage
(CMOS input)
Data
,
DE
,
VSYNC
,
HSYNC, and IDCK+/−
0.5 V ≤ V
REF
≤ 0.95 V V
REF
− 0.2
V
V
IL
(CMOS i
npu
t)
Other inputs 0.3V
DD
V
V
OH
High-level digital output voltage (open-drain output) V
DD
= 3 V, I
OH
= 20 μA 2.4 V
V
OL
Low-level digital output voltage (open-drain output) V
DD
= 3.6 V, I
OL
= 4 mA 0.4 V
I
IH
High-level input current V
I
= 3.6 V ±50 μA
I
IL
Low-level input current V
I
= 0 ±50 μA
V
H
DVI single-ended high-level output voltage
AV
DD
= 3.3 V ± 5%,
R
T
†
= 50 Ω ± 10%,
R
TFADJ
= 510 Ω ± 1%
AV
DD
− 0.01 AV
DD
+ 0.01 V
V
L
DVI single-ended low-level output voltage
AV
DD
= 3.3 V ± 5%,
R
T
†
= 50 Ω ± 10%,
R
TFADJ
= 510 Ω ± 1%
AV
DD
− 0.6 AV
DD
− 0.4 V
V
SWING
DVI single-ended output swing voltage
AV
DD
= 3.3 V ± 5%,
R
T
†
= 50 Ω ± 10%,
R
TFADJ
= 510 Ω ± 1%
400 600 mV
P-P
V
OFF
DVI single-ended standby/off output voltage
AV
DD
= 3.3 V ± 5%,
R
T
†
= 50 Ω ± 10%,
R
TFADJ
= 510 Ω ± 1%
AV
DD
− 0.01 AV
DD
+ 0.01 V
I
PD
Power-down current (see Note 1) 200 500 μA
I
IDD
Normal power-supply current Worst-case pattern
‡
200 250 mA
†
R
T
is the single-ended termination resistance at the receiver end of the DVI link.
‡
Black and white checkerboard pattern, each checker is one pixel wide.
NOTE 1: Assumes all inputs to the transmitter are not toggling.