Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
MSEN/PO1 11 O
Monitor sense/programmable output 1. The operation of this pin depends on whether the I
2
C interface
is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ
pullup resistor connected to V
DD
is required on this pin.
When I
2
C is disabled (ISEL = low), a high level indicates a powered-on receiver is detected at the
differential outputs. A low level indicates a powered-on receiver is not detected. This function is valid
only in dc-coupled systems.
When I
2
C is enabled (ISEL = high), this output is programmable through the I
2
C interface (see the I
2
C
register descriptions section).
PD 10 I
Power down (active low). In the power-down state, only the digital I/O buffers and I
2
C interface remain
active.
When I
2
C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects
the power-down mode.
When I
2
C is enabled (ISEL = high), the power-down state is selected through I
2
C. In this configuration,
PD
should be tied to GND.
Note: The default register value for PD
is low, so the device is in power-down mode when I
2
C is first
enabled or after an I
2
C reset.
V
REF
3 I
Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,
VSYNC, and IDCK±).
For high-swing 3.3-V input signal levels, V
REF
should be tied to V
DD
.
For low-swing input signal levels, V
REF
should be set to half of the maximum input voltage level. See
the recommended operating conditions section for the allowable range for V
REF
.
The desired V
REF
voltage level is typically derived using a simple voltage-divider circuit.
Reserved
RESERVED 34 In This pin is reserved and must be tied to GND for normal operation.
DVI Differential Signal Output
TFADJ 19 I
Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the
value of the pullup resistor R
TFADJ
connected to TV
DD
.
TX0+
TX0−
25
24
O
Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video and
HSYNC and VSYNC during the blanking interval.
TX1+
TX1−
28
27
O
Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and
CTL[1] during the blanking interval.
TX2+
TX2−
31
30
O
Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and
CTL[3:2] during the blanking interval.
TXC+
TXC−
22
21
O DVI differential output clock
Power and Ground
DGND 16, 48, 64 Ground Digital ground
DV
DD
1, 12, 33 Power Digital power supply. Must be set to 3.3-V nominal.
NC 49 NC No connection required. If connected, tie high.
PGND 17 Ground PLL ground
PV
DD
18 Power PLL power supply. Must be set to 3.3-V nominal.
TGND 20, 26, 32 Ground Transmitter differential output driver ground
TV
DD
23, 29 Power Transmitter differential output driver power supply. Must be set to 3.3-V nominal.