Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
DE 2 I
Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel
data or control data on any given input clock cycle. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes
HSYNC, VSYNC, and CTL[3:1].
HSYNC 4 I Horizontal sync input
IDCK−
IDCK+
56
57
I
Differential clock input. The TFP410 supports both single-ended and fully differential clock input
modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the
single-ended clock source and the IDCK− input (pin 56) should be tied to GND. In the differential clock
input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK− signals as the timing
reference for latching incoming data DATA[23:0], DE, HSYNC, and VSYNC. The differential clock input
mode is only available in the low signal swing mode.
VSYNC 5 I Vertical sync input
Configuration/Programming
BSEL/SCL 15 I
Input bus select/I
2
C clock input. The operation of this pin depends on whether the I
2
C interface is
enabled or disabled. This pin is only 3.3-V tolerant.
When I
2
C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level
selects 12-bit input, dual-edge input mode.
When I
2
C is enabled (ISEL = high), this pin functions as the I
2
C clock input (see the I
2
C register
descriptions section). In this configuration, this pin has an open-drain output that requires an external
5-kΩ pullup resistor connected to V
DD
.
DKEN 35 I
Data deskew enable. The deskew function can be enabled either through I
2
C or by this pin when I
2
C is
disabled. When deskew is enabled, the input clock to data setup/hold time can be adjusted in discrete
trim increments. The amount of trim per increment is defined by t
(STEP)
.
When I
2
C is disabled (ISEL = low), a high level enables deskew with the trim increment determined by
pins DK[3:1] (see the data deskew section). A low level disables deskew and the default trim setting is
used.
When I
2
C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I
2
C.
In this configuration, the DKEN pin should be tied to either GND or V
DD
to avoid a floating input.
DSEL/SDA 14 I/O
DSEL/I
2
C data. The operation of this pin depends on whether the I
2
C interface is enabled or disabled.
This pin is only 3.3-V tolerant.
When I
2
C is disabled (ISEL = low), this pin is used with BSEL and V
REF
to select the single-ended or
differential input clock mode (see the universal graphics controller interface modes section).
When I
2
C is enabled (ISEL = high), this pin functions as the I
2
C bidirectional data line. In this
configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor
connected to V
DD
.
EDGE/HTPLG 9 I
Edge select/hot plug input. The operation of this pin depends on whether the I
2
C interface is enabled or
disabled. This input is 3.3-V tolerant only.
When I
2
C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of
the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock
IDCK+. This is the case for both single-ended and differential input clock modes.
When I
2
C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal (see the DVI or
VESA™ P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ
resistor.
ISEL/RST 13 I
I
2
C interface select/I
2
C reset (active low, asynchronous)
If ISEL is high, the I
2
C interface is active. Default values for the I
2
C registers can be found in the I
2
C
register descriptions section.
If ISEL is low, I
2
C is disabled and the chip configuration is specified by the configuration pins (BSEL,
DSEL, EDGE, V
REF
) and state pins (PD, DKEN).
If ISEL is brought low and then back high, the I
2
C state machine is reset. The register values are
changed to their default values and are not preserved from before the reset.