Datasheet

TFP410-EP
PanelBus™ DIGITAL TRANSMITTER
SGLS344A − JULY 2006 − REVISED MAY 2011
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
CC
or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
pin assignments
12 3
TGND
TX2+
TX2−
TV
DD
TX1+
TX1−
TGND
TX0+
TX0−
TV
DD
TXC+
TXC−
TGND
TFADJ
PV
DD
PGND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
NC
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
IDCK−
IDCK+
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DGND
5678
47 46 45 44 4348 42 40 39 3841
910111213
37 36 35 34 33
14 15 16
PAP PACKAGE
(TOP VIEW)
DGND DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DKEN RESERVED DV
DD
DV
DD
DE
V
REF
HSYNC
VSYNC
A3/DK3
CTL2/A2/DK2 CTL1/A1/DK1
EDGE/HTPLG
PD
MSEN/PO1
DV
DD
ISEL/RST
DSEL/SDA
BSEL/SCL
DGND