Information

TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
80%
20%
80%
20%
t
r(2)
t
f(2)
ODCK
Figure 1. Rise and Fall Time of ODCK
80% 80%
20% 20%
t
r(1)
t
f(1)
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
Figure 2. Rise and Fall Time of Data and Control Signals
f
(ODCK)
ODCK
Figure 3. ODCK Frequency
t
su(1)
t
h(1)
t
su(2)
t
h(2)
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
ODCK
QE(0-23), QO(0-23), DE
CTL(1-2), HSYNC, VSYNC
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
Figure 5. ODCK High to QE[23:0]
Staggered Data Output
Figure 6. Analog Input Intra-Pair
Differential Skew
50%
V
OH
t
d
ODCK
QE(O-23)
50%
t
(ps)
Tx+
Tx-