Information
TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ID(2)
Differential input sensitivity
†
150 1560 mV
p-p
t
ps
Analog input intra-pair (+ to -) differential skew (see Note 6) 0.4 t
bit
‡
t
(ccs)
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
Analog Input inter-pair or channel-to-channel skew
(see Note 6)
1 t
pix
§
t
(ijit)
Worse case differential input clock jitter tolerance
¶
(see Note 6)
Worse case differential input clock jitter tolerance
¶
(see Note 6)
50 ps
t
f(1)
Fall time of data and control signals
#,
||
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
2.4
1.9
ns
t
r(1)
Rise time of data and control signals
#,
||
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
2.4
1.9
ns
t
r(2)
Rise time of ODCK clock
#
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
2.4
1.9
ns
t
f(2)
Fall time of ODCK clock
#
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
2.4
1.9
ns
t
su(1)
Setup time, data, and control
signal to falling edge of ODCK
1 pixel, OCK_INV = low
||
,
PIXS = low
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
1.0 ns
Hold time data and control
1 pixel OCK INV = low
||
ST = Low C
L
= 5 pF
t
h(1)
H
o
ld
t
i
me,
d
ata,
an
d
contro
l
i l t f lli d f ODCK
1
p
i
xe
l
,
OCK
_
INV
=
l
ow
||
,
PIXS l
ST
=
L
ow,
C
L
=
5
p
F
ST Hi h C 10 F
1.0
ns
t
h(1)
signal to falling edge of ODCK PIXS = low ST = High, C
L
= 10 pF
1
.
0
ns
Setup time data and control
1 pixel OCK INV = high
||
ST = Low C
L
= 5 pF
t
su(2)
S
etup
t
i
me,
d
ata,
an
d
contro
l
i l t i i d f ODCK
1
p
i
xe
l
,
OCK
_
INV
=
hi
g
h
||
,
PIXS l
ST
=
L
ow,
C
L
=
5
p
F
ST Hi h C 10 F
1.0
ns
t
su(2)
signal to rising edge of ODCK PIXS = low ST = High, C
L
= 10 pF
1
.
0
ns
t
h(2)
Hold time, data, and control
signal to rising edge of ODCK
2 pixel and STAG
OCK_INV = high
||
PIXS = high
ST = Low, C
L
= 5 pF
ST = High, C
L
= 10 pF
0.5 ns
f
ODCK frequency
PIX = Low (1-PIX/CLK) 25 165
MHz
f
(ODCK)
ODCK frequency
PIX = High (2-PIX/CLK) 12.5 82.5
MHz
ODCK duty-cycle 40% 50% 60%
t
pd(PDL)
Propagation delay time from PD low to Hi-Z outputs 9 ns
t
pd(PDOL)
Propagation delay time from PDO low to Hi-Z outputs 9 ns
t
t(HSC)
Transition time between DE transition to SCDT low
k
1e6 t
pix
t
t(FSC)
Transition time between DE transition to SCDT high
k
1600 t
pix
t
d
Delay time, ODCK latching edge to QE[23:0] data output
STAG = Low
Pixs = High
0.5 t
pix
†
Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
‡
t
bit
is 1/10 the pixel time, tpix
§
t
pix
is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t
pix
in 1-pixel/clock mode or 2t
pix
when in
2-pixel/clock mode.
¶
Measured differentially at 50% crossing using ODCK output clock as trigger.
#
Rise and fall times measured as time between 20% and 80% of signal amplitude.
||
Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1]
kLink active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
NOTE 6: By characterization