Information

TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP403 TMDS input levels and input impedance matching (continued)
_
+
Internal
Termination at 50 Ω
AVDD
DVI Compliant Cable
DATA
DATA
TI TFP403
Receiver
DVI
Transmitter
Current
Source
Figure 12. TMDS Differential Input and Transmitter Connection
1/2 V
ID
AVCC
AVCC −1/2 V
ID
+ 1/2 V
ID
−1/2 V
ID
V
ID
a ) Single-Ended Input Signal
b) Differential Input Signal
Figure 13. TMDS Inputs
TFP403 modes of operation
The TFP403 provides systems design flexibility and value by providing the system designer with configurable
options or modes of operation to support varying system architectures. The following table outlines the various
panel modes that can be supported along with appropriate external control pin settings.
PANEL PIXEL RATE
ODCK LATCH
EDGE
ODCK DFO PIXS OCK_INV
TFT or 16-bit DSTN 1 pix/clock Falling Free run 0 0 0
TFT or 16-bit DSTN 1 pix/clock Rising Free run 0 0 1
TFT 2 pix/clock Falling Free run 0 1 0
TFT 2 pix/clock Rising Free run 0 1 1
24-bit DSTN 1 pix/clock Falling Gated low 1 0 0
NONE 1 pix/clock Rising Gated low 1 0 1
24-bit DSTN 2 pix/clock Falling Gated low 1 1 0
24-bit DSTN 2 pix/clock Rising Gated low 1 1 1