Information

TFP403
TI PanelBus™ DIGITAL RECEIVER
SLDS125B − DECEMBER 2000 − REVISED MAY 2011
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 7. Delay From PD Low to Hi-Z Outputs Figure 8. Delay From PDO Low to Hi-Z Outputs
PD
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-2),
HSYNC, VSYNC, SCDT
t
pd(PDL)
PDO
QE(0-23), QO(0-23),
ODCK, DE, CTL2,
HSYNC, VSYNC
t
pd(PDOL)
V
IL
V
IL
Figure 9. Analog Input Channel-to-Channel Skew
t
(ccs)
50%
50%
TX2
TX1
TX0
t
t(HSC)
t
t(FSC)
DE
SCDT
Figure 10. Time Between DE Transitions to SCDT Low and SCDT High
t
(DEL)
t
(DEH)
DE
Figure 11. Minimum DE Low and Maximum DE High