Information
TFP401
TFP401A
www.ti.com
SLDS120E –MARCH 2000–REVISED JULY 2013
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O DESCRIPTION
NAME NO.
Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal
Rx1+ 85 AI differential input pair
Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.
Channel-1 negative receiver input – Negative side of channel-1 TMDS low-voltage signal
Rx1– 86 AI
differential input pair
Channel-2 positive receiver input – Positive side of channel-2 TMDS low-voltage signal
Rx2+ 80 AI differential input pair
Channel-2 receives red-pixel data in active display and CTL2, CTL3 control signals in blank.
Channel-2 negative receiver input – Negative side of channel-2 TMDS low-voltage signal
Rx2– 81 AI
differential input pair
Sync detect - Output to signal when the link is active or inactive. The link is considered to be
active when DE is actively switching. The TFP401/401A monitors the state of DE to
determine link activity. SCDT can be tied externally to PDO to power down the output drivers
SCDT 8 DO
when the link is inactive.
High: Active link
Low: Inactive link
Output drive strength select – Selects output drive strength for high- or low-current drive.
(See dc specifications for I
OH
and I
OL
vs ST state).
ST 3 DI
High: High drive strength
Low: Low drive strength
Staggered pixel select – An active-low signal used in the 2-pixel/clock pixel mode (PIXS =
high). Time-staggers the even and odd pixel outputs to reduce ground bounce. Normal
STAG 7 DI operation outputs the odd and even pixels simultaneously.
High: Normal simultaneous even/odd pixel output
Low: Time-staggered even/odd pixel output
VSYNC 47 DO Vertical sync output
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
DV
DD
, AV
DD
, OV
DD
,
Supply voltage range –0.3 4 V
PV
DD
V
I
Input voltage range, logic/analog signals –0.3 4 V
Operating ambient temperature range 0 70 °C
T
stg
Storage temperature range –65 150 °C
Soldered
(2)
4.3
Package power
W
dissipation/PowerPAD package
Not soldered
(3)
2.7
ESD protection, all pins Human-body model 2.5 kV
JEDEC latchup (EIA/JESD78) 100 mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Specified with PowerPAD bond pad on the backside of the package soldered to a 2-oz. (0.071-mm thick) Cu plate PCB thermal plane.
Specified at maximum allowed operating temperature, 70°C.
(3) PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70°C.
THERMAL INFORMATION
TFP401, TFP401A
THERMAL METRIC
(1)
PZP UNIT
100 PINS
θ
JA
Junction-to-ambient thermal resistance 26 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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