Information

_
+
Latch
Channel 2
_
+
Latch
Channel 1
_
+
Latch
Channel 0
_
+
PLL
Data Recovery
and
Synchronization
TMDS
Decoder
CH2(0-9)
CH1(0-9)
CH0(0-9)
Panel
Interface
RED(0-7)
CTL3
CTL2
GRN(0-7)
CTL1
BLU(0-7)
VSYNC
HSYNC
QE(0-23)
QO(0-23)
ODCK
DE
SCDT
CTL3
CTL2
CTL1
VSYNC
HSYNC
1.8 V
Regulator
3.3 V
Internal 50-Ω
Termination
3.3 V
3.3 V
Rx2+
Rx2-
Rx1+
Rx1-
Rx0+
Rx0-
RxC+
RxC-
TFP401
TFP401A
www.ti.com SLDS120E –MARCH 2000–REVISED JULY 2013
FUNCTIONAL BLOCK DIAGRAM
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
AGND 79, 83, 87, 89, 92 GND Analog ground – Ground reference and current return for analog circuitry
AV
DD
82, 84, 88, 95 V
DD
Analog V
DD
– Power supply for analog circuitry. Nominally 3.3 V
General-purpose control signals – Used for user-defined control. CTL1 is not powered down
CTL[3:1] 42, 41, 40 DO
via PDO.
Output data enable – Used to indicate time of active video display versus non-active display
or blank time. During blank, only HSYNC, VSYNC, and CTL[3:1] are transmitted. During
DE 46 DO times of active display, or non-blank, only pixel data, QE[23:0], and QO[23:0] are transmitted.
High: Active display time
Low: Blank time
Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN
panel support. For TFT support, the ODCK clock runs continuously. For DSTN support,
DFO 1 DI ODCK only clocks when DE is high; otherwise, ODCK is held low when DE is low.
High: DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.
DGND 5, 39, 68 GND Digital ground – Ground reference and current return for digital core
DV
DD
6, 38, 67 V
DD
Digital V
DD
– Power supply for digital core. Nominally 3.3 V
Internal impedance matching – The TFP401/401A is internally optimized for impedance
EXT_RES 96 AI
matching at 50 Ω. An external resistor tied to this pin has no effect on device performance.
HSYNC 48 DO Horizontal sync output
RSVD 99 DI Reserved. Must be tied high for normal operation
OV
DD
18, 29, 43, 57, 78 V
DD
Output driver V
DD
– Power supply for output drivers. Nominally 3.3 V
Output data clock – Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock
ODCK 44 DO
mode), along with DE, HSYNC, VSYNC and CTL[3:1], are synchronized to this clock.
OGND 19, 28, 45, 58, 76 GND Output driver ground – Ground reference and current return for digital output drivers
ODCK polarity – Selects ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and
control signals (HSYNC, VSYNC, DE, CTL[3:1]) are latched.
OCK_INV 100 DI Normal mode:
High: Latches output data on rising ODCK edge
Low: Latches output data on falling ODCK edge
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