Information
AVCC
AVCC – 1/2 VIDIFF
1/2 VIDIFF
a) Single-Ended Input Signal
+1/2 VIDIFF
–1/2 VIDIFF
VIDIFF
b) Differential Input Signal
_
+
Internal Termination
at 50 Ω
AVDD
DVI Compliant Cable
DATA
DATA
TI TFP401/401A
Receiver
DVI
Transmitter
Current
Source
TFP401
TFP401A
SLDS120E –MARCH 2000–REVISED JULY 2013
www.ti.com
TFP401/401A TMDS INPUT LEVELS AND INPUT IMPEDANCE MATCHING
The TMDS inputs to the TFP401/401A receiver have a fixed single-ended termination to AV
DD
. The
TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The
device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with
current sockets. The fixed impedance eliminates the need for an external resistor while providing optimum
impedance matching to standard 50-Ω DVI cables.
Figure 14 shows a conceptual schematic of a DVI transmitter and TFP401/401A receiver connection. A
transmitter drives the twisted-pair cable via a current source, usually achieved with an open-drain type output
driver. The internal resistor, which is matched to the cable impedance at the TFP401/401A input, provides a
pullup to AV
DD
. Naturally, when the transmitter is disconnected and the TFP401/401A DVI inputs are left
unconnected, the TFP401/401A receiver inputs pull up to AV
DD
. The single-ended differential signal and full-
differential signal is shown in Figure 15. The TFP401/401A is designed to respond to differential signal swings
ranging from 150 mV to 1.56 V with common-mode voltages ranging from (AV
DD
– 300 mV) to (AV
DD
– 37 mV).
Figure 14. TMDS Differential Input and Transmitter Connection
Figure 15. TMDS Inputs
TFP401A INCORPORATES HSYNC JITTER IMMUNITY
Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals
during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal
in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and
if the position of HSYNC shifts continuously, the receiver can lose track of the input timing, causing pixel noise to
occur on the display. For this reason, a DVI-compliant receiver with HSYNC jitter immunity should be used in all
displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.
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