Information

TFP401
TFP401A
www.ti.com SLDS120E –MARCH 2000–REVISED JULY 2013
requires a TMDS-compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same
24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to
the flat-panel drive circuitry to produce an image on the display. Because the host and display can be separated
by distances up to 5 meters or more, serial transmission of the pixel data is preferred. To support modern display
resolutions up to UXGA, a high-bandwidth receiver with good jitter and skew tolerance is required.
TMDS PIXEL DATA AND CONTROL SIGNAL ENCODING
TMDS stands for transition-minimized differential signaling. Only one of two possible TMDS characters for a
given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros
previously sent, and transmits the character that minimizes the number of transitions to approximate a dc
balance of the transmission line.
Three TMDS channels are used to receive RGB pixel data during active display time, DE = high. The same three
channels also receive control signals, HSYNC, VSYNC, and user-defined control signals CTL[3:1]. These control
signals are received during inactive display or blanking-time. Blanking-time is when DE = low. The following table
maps the received input data to the appropriate TMDS input channel in a DVI-compliant system.
RECEIVED PIXEL DATA OUTPUT PINS
INPUT CHANNEL
ACTIVE DISPLAY DE = HIGH (VALID FOR DE = HIGH)
Red[7:0] Channel-2 (Rx2 ±) QE[23:16] QO[23:16]
Green[7:0] Channel-1 (Rx1 ±) QE[15:8] QO[15:8]
Blue[7:0] Channel-0 (Rx0 ±) QE[7:0] QO[7:0]
RECEIVED CONTROL DATA OUTPUT PINS
INPUT CHANNEL
BLANKING DE = LOW (VALID FOR DE = LOW)
CTL[3:2] Channel-2 (Rx2 ±) CTL[3:2]
CTL[1: 0]
(1)
Channel-1 (Rx1 ±) CTL1
HSYNC, VSYNC Channel-0 (Rx0 ±) HSYNC, VSYNC
(1) Some TMDS transmitters transmit a CTL0 signal. The TFP401/401A decodes and transfers CTL[3:1]
and ignores CTL0 characters. CTL0 is not available as a TFP401/401A output.
The TFP401/401A discriminates between valid pixel TMDS characters and control TMDS characters to
determine the state of active display versus blanking, i.e., the state of DE.
TFP401/401A CLOCKING AND DATA SYNCHRONIZATION
The TFP401/401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time,
t
pix
. The frequency of this clock is also referred to as the pixel rate. Because the TMDS encoded data on Rx[2:0]
contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate. For example, the
required pixel rate to support a UXGA resolution with 60-Hz refresh rate is 165 MHz. The TMDS serial bit rate is
10× the pixel rate, or 1.65 Gb/s. Due to the transmission of this high-speed digital bit stream, on three separate
channels (or twisted-pair wires) of long distances (3–5 meters), phase synchronization between the data steams
and the input reference clock is not assured. In addition, skew between the three data channels is common. The
TFP401/401A uses a 4× oversampling scheme of the input data streams to achieve reliable synchronization with
up to 1-t
pix
channel-to-channel skew tolerance. Accumulated jitter on the clock and data lines due to reflections
and external noise sources is also typical of high-speed serial data transmission; hence, the TFP401/401A
design for high jitter tolerance.
The input clock to the TFP401/401A is conditioned by a phase-locked loop (PLL) to remove high-frequency jitter
from the clock. The PLL provides four 10× clock outputs of different phase to locate and sync the TMDS data
streams (4× oversampling). During active display, the pixel data is encoded to be transition-minimized, whereas
in blank, the control data is encoded to be transition-maximized. A DVI-compliant transmitter is required to
transmit in blank for a minimum period of time, 128 t
pix
, to ensure sufficient time for data synchronization when
the receiver sees a transition-maximized code. Synchronization during blank, when the data is transition-
maximized, ensures reliable data-bit boundary detection. Phase synchronization to the data streams is unique for
each of the three input channels and is maintained as long as the link remains active.
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