Information

t
DEL
t
DEH
DE
t
t(HSC)
t
t(FSC)
DE
SCDT
t
ccs
50%
50%
TX2
TX1
TX0
DFO, ST, PIXS, STAG,
Rx[2:0]+, Rx[2:0]–,
OCK_INV
PD
V
IH
t
p(PDH-V)
t
wL(PDL_MIN)
PD
V
IL
TFP401
TFP401A
SLDS120E –MARCH 2000–REVISED JULY 2013 www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 9. Delay From PD Low to High Figure 10. Minimum Time PD Low
Before Inputs Are Active N
N N
N
Figure 11. Analog Input Channel-to-Channel Skew
N
N
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
N
N
Figure 13. Minimum DE Low and Maximum DE High
DETAILED DESCRIPTION
FUNDAMENTAL OPERATION
The TFP401/401A is a digital visual interface (DVI)-compliant TMDS digital receiver that is used in digital flat
panel display systems to receive and decode TMDS-encoded RGB pixel data streams. In a digital display system
a host, usually a PC or workstation, contains a TMDS-compatible transmitter that receives 24-bit pixel data along
with appropriate control signals and encodes them into a high-speed low-voltage differential serial bit stream fit
for transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor,
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