Datasheet

80% 80%
20% 20%
t
r1
t
f1
QE(0-23), QO(0-23), DE
CTK(1-3), HSYNC, VSYNC
80%
20%
80%
20%
t
r2
t
f2
ODCK
f
ODCK
ODCK
t
(su1)
t
(h1)
t
(su2)
t
(h2)
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
ODCK
QE(0-23), QO(0-23), DE
CTL(1-3), HSYNC, VSYNC
OCK_INV
50%
V
OH
t
d(st)
ODCK
QE(O-23)
PD
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-3),
HSYNC, VSYNC, SCDT
t
pd(PDL)
V
IL
TFP401A-EP
www.ti.com SLDS160A –MARCH 2009– REVISED JULY 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Rise and Fall TIme of Data and Control Signals
Figure 2. Rise and Fall Time of ODCK
Figure 3. ODCK Frequency
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
Figure 5. ODCK High to QE[23:0] Staggered Data Output
Figure 6. Analog Input Intra-Pair Differential Skew
Figure 7. Delay from PD Low to Hi-Z Outputs
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