Datasheet

TFP401A-EP
www.ti.com SLDS160A –MARCH 2009– REVISED JULY 2011
AC ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
ID
(2) Differential input sensitivity
(1)
150 1560 mV
p-p
t
ps
Analog input intra-pair (+ to -) 0.4 t
bit
(3)
differential skew
(2)
t
ccs
Analog Input inter-pair or 1
t
pix
(4)
channel-to-channel skew
(2)
t
ijit
Worse case differential input clock 50
ps
jitter tolerance
(5)
,
(2) (6)
t
f1
Fall time of data and control ST = Low, CL=5 pF 2.4
ns
signals
(7)
,
(8) (6)
ST = High, CL=10 pF 1.9
t
r1
Rise time of data and control ST = Low, CL=5 pF 2.4
ns
signals
(7)
,
(8) (6)
ST = High, CL=10 pF 1.9
t
r2
Rise time of ODCK clock
(7) (6)
ST = Low, CL=5 pF 2.4
ns
ST = High, CL=10 pF 1.9
t
f2
Fall time of ODCK clock
(7) (6)
ST = Low, CL=5 pF 2.4
ns
ST = High, CL=10 pF 1.9
t
su1
Setup time, data and control signal to 1 pixel/clock, PIXS = low, 1.8
falling edge of ODCK
(6)
OCK_INV = low
2 pixel/clock, PIXS = high, 3.8
ns
STAG = high, OCK_INV = low
2 pixel and STAG, PIXS = high, 0.6
STAG = low, OCK_INV = low
t
h1
Hold time, data and control signal to 1 pixel/clock, PIXS = low, 0.6
falling edge of ODCK
(6)
OCK_INV = low
2 pixel and STAG, PIXS = high, 2.5
ns
STAG = low, OCK_INV = low
2 pixel/clock, PIXS = high, 2.9
STAG = high, OCK_INV = low
t
su2
Setup time, data and control signal to 1 pixel/clock, PIXS = low, 2.1
rising edge of ODCK
(6)
OCK_INV = high
2 pixel/clock, PIXS = high, 4
ns
STAG = high, OCK_INV = high
2 pixel and STAG, PIXS = high, 1.5
STAG = low, OCK_INV = high
t
h2
Hold time, data and control signal to 1 pixel/clock, PIXS = low, 0.3
rising edge of ODCK
(6)
OCK_INV = high
2 pixel and STAG, PIXS = high, 2.4
ns
STAG = low, OCK_INV = high
2 pixel/clock, PIXS = high, 2.1
STAG = high, OCK_INV = high
f
ODCK
ODCK frequency PIX = Low (1-PIX/CLK) 25 165
MHz
PIX = High (2-PIX/CLK) 12.5 82.5
ODCK duty-cycle 45% 60% 75%
t
pd(PDL)
Propagation delay time from PD low 9 ns
to Hi-Z outputs
(6)
(1) Specified as ac parameter to include sensitivity to overshoot, undershoot and reflection.
(2) By characterization
(3) t
bit
is 1/10 the pixel time, t
pix
(4) t
pix
is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t
pix
in 1-pixel/clock mode or 2t
pix
when
in 2-pixel/clock mode.
(5) Measured differentially at 50% crossing using ODCK output clock as trigger.
(6) Not Production Test
(7) Rise and fall times measured as time between 20% and 80% of signal amplitude.
(8) Data and control signals are : QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[3:1]
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