Datasheet

Internal Termination

at 50 Ω

AVDD

DVI Compliant Cable

DATA

TI TFP401/401A

Receiver

DVI

Transmitter

Current

Source

1/2 VIDIFF

AVCC

AVCC - 1/2 VIDIFF

a ) Single-Ended Input Signal

+ 1/2 VIDIFF

- 1/2 VIDIFF

VIDIFF

b) Differential Input Signal

TFP401A-EP

www.ti.com

SLDS160A –MARCH 2009– REVISED JULY 2011

Figure 14. TMDS Differential Input and Transmitter Connection

Figure 15. TMDS Inputs

TFP401A INCORPORATES HSYNC JITTER IMMUNITY

Several DVI transmitters available in the market introduce jitter on the transmitted HSYNC and VSYNC signals

during the TMDS encryption process. The HSYNC signal can shift by one pixel position (one clock) from nominal

in either direction, resulting in up to two cycles of HSYNC shift. This jitter carries through to the DVI receiver, and

if the position of HSYNC shifts continuously, the receiver can lose track of the input timing and pixel noise will

occur on the display. For this reason, a DVI compliant receiver with HSYNC jitter immunity should be used in all

displays that could be connected to host PCs with transmitters that have this HSYNC jitter problem.

The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant

transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the

location of HSYNC. The TFP401A receiver uses the DE and clock signals recreate stable vertical and horizontal

sync signals. The circuit filters the HSYNC output of the receiver, and HSYNC is shifted to the nearest eighth bit

boundary, producing a stable output with respect to data, as shown in Figure 16. This will ensure accurate data

synchronization at the input of the display timing controller.