Datasheet

 
 PanelBus  
SLDS119C - MARCH 2000 − REVISED OCTOBER 2003
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
PD
QE(0-23), QO(0-23),
ODCK, DE, CTL(1-3),
HSYNC, VSYNC, SCDT
t
pd(PDL)
PDO
QE(0-23), QO(0-23),
ODCK, DE, CTL(2-3),
HSYNC, VSYNC
t
pd(PDOL)
V
IL
V
IL
Figure 7. Delay From PD Low to Hi-Z Outputs Figure 8. Delay From PDO Low to Hi-Z Outputs
PD
DFO, ST, PIXS, STAG,
Rx(0-2)+, Rx(0-2)-,
OCK_INV
V
IH
t
p(PDH-V)
t
wL(PDL_MIN)
PD
Figure 9. Delay From PD Low to High Before
Inputs are Active
Figure 10. Minimum Time PD Low
V
IL
t
ccs
50%
50%
TX2
TX1
TX0
Figure 11. Analog Input Channel-to-Channel Skew
t
t(HSC)
t
t(FSC)
DE
SCDT
Figure 12. Time Between DE Transitions to SCDT Low and SCDT High
t
DEL
t
DEH
DE
Figure 13. Minimum DE Low and Maximum DE High
Not Recommended for New Designs