Datasheet

 
 PanelBus  
SLDS119C - MARCH 2000 − REVISED OCTOBER 2003
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
80% 80%
20% 20%
t
r1
t
f1
QE(0-23), QO(0-23), DE
CTK(1-3), HSYNC, VSYNC
Figure 1. Rise and Fall TIme of Data and Control Signals
80%
20%
80%
20%
t
r2
t
f2
ODCK
Figure 2. Rise and Fall Time of ODCK
f
ODCK
ODCK
Figure 3. ODCK Frequency
t
(su1)
t
(h1)
t
(su2)
t
(h2)
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
V
OH
V
OL
ODCK
QE(0-23), QO(0-23), DE
CTL(1-3), HSYNC, VSYNC
OCK_INV
Figure 4. Data Setup and Hold Time to Rising and Falling Edge of ODCK
50%
50%
V
OH
t
d(st)
t
ps
Tx+
Tx-
ODCK
QE(O-23)
Figure 5. ODCK High to QE[23:0]
Staggered Data Output
Figure 6. Analog Input Intra-Pair
Differential Skew
Not Recommended for New Designs