Datasheet

14
I/O
Port
Shift
Register
8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
2
1
13
16
8
GND
V
CC
SDA
SCL
A1
A0
INT
I
2
C Bus
Control
P7−P0
3
A2
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity
Pulse
Data From
Shift Register
Output Port
Register
Configuration
Register
Input Port
Register
Polarity
Inversion
Register
Polarity
Register Data
Input Port
Register Data
GND
P0 to P7
V
CC
Output Port
Register Data
Q1
Q2
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
D
C
K
FF
Q
Q
INT
100 kW
TCA9554
www.ti.com SCPS233A –NOVEMBER 2011–REVISED MARCH 2012
Figure 1. FUNCTIONAL BLOCK DIAGRAM
A. Pin numbers shown are for the PW package.
B. All I/Os are set to inputs at reset.
Figure 2. SIMPLIFIED SCHEMATIC OF P0 TO P7
A. At power-on reset, all registers return to default values.
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