Datasheet

1 2 3 4 5 6 7 8 9
S 0 1 0 0 A2 A1 A0 1 A A A A 1 P
R/W
SCL
SDA
INT
00 10 03
12
11 12
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
Data 02Data 01Data 00 Data 03
DataDataData 10
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
t
ph
t
iv
t
ir
t
ph
t
ps
t
ps
I0.x I1.x I0.x I1.x
TCA9535
SCPS201A –AUGUST 2009– REVISED SEPTEMBER 2009 www.ti.com
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A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 9 for these details).
Figure 11. Read Input Port Register, Scenario 2
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