Datasheet
TCA8418
SCPS215B –SEPTEMBER 2009–REVISED MARCH 2010
www.ti.com
I
2
C INTERFACE TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 13)
STANDARD MODE FAST MODE FAST MODE PLUS (FM+)
I
2
C BUS I
2
C BUS I
2
C BUS
UNIT
MIN MAX MIN MAX MIN MAX
f
scl
I
2
C clock frequency 0 100 0 400 0 1000 kHz
t
sch
I
2
C clock high time 4 0.6 0.26 ms
t
scl
I
2
C clock low time 4.7 1.3 0.5 ms
t
sp
I
2
C spike time 50 50 50 ns
t
sds
I
2
C serial data setup time 250 100 50 ns
t
sdh
I
2
C serial data hold time 0 0 0 ns
t
icr
I
2
C input rise time 1000 20 + 0.1C
b
(1)
300 120 ns
t
icf
I
2
C input fall time 300 20 + 0.1C
b
(1)
300 120 ns
t
ocf
I
2
C output fall time; 10 pF to 400 pF bus 300 20 + 0.1C
b
(1)
300 120 ms
I
2
C bus free time between Stop and
t
buf
4.7 1.3 0.5 ms
Start
I
2
C Start or repeater Start condition
t
sts
4.7 0.6 0.26 ms
setup time
I
2
C Start or repeater Start condition hold
t
sth
4 0.6 0.26 ms
time
t
sps
I
2
C Stop condition setup time 4 0.6 0.26 ms
Valid data time; SCL low to SDA output
t
vd(data)
1 0.9 0.45 ms
valid
Valid data time of ACK condition; ACK
t
vd(ack)
1 0.9 0.45 ms
signal from SCL low to SDA (out) low
(1) C
b
= total capacitance of one bus line in pF
RESET TIMING REQUIREMENTS
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 16)
STANDARD MODE, FAST
MODE, FAST MODE PLUS
(FM+)
UNIT
I
2
C BUS
MIN MAX
t
W
Reset pulse duration 120
(1)
ms
t
REC
Reset recovery time 120
(1)
ms
t
RESET
Time to reset 120
(1)
ms
(1) The GPIO debounce circuit uses each GPIO input which passes through a two-stage register circuit. Both registers are clocked by the
same clock signal, presumably free-running, with a nominal period of 50uS. When an input changes state, the new state is clocked into
the first stage on one clock transition. On the next same-direction transition, if the input state is still the same as the previously clocked
state, the signal is clocked into the second stage, and then on to the remaining circuits. Since the inputs are asynchronous to the clock,
it will take anywhere from zero to 50 msec after the input transition to clock the signal into the first stage. Therefore, the total debounce
time may be as long as 100 msec. Finally, to account for a slow clock, the spec further guard-banded at 120 msec.
6 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TCA8418