Datasheet

1 2
SCL
3 4 5 6 7 8
SDA
A A A
Data 1
R/W
9
00 0 0 0 0 0
1
0.0
P
S
0
1
0 0 0 0
AD
DR
0
Slave Address
Command Byte
Data to Port
Start Condition
Acknowledge
From Slave
Write to Port
Data Out
from Port
Data Valid
Acknowledge
From Slave
Acknowledge
From Slave
t
pv
1 2
SCL
3
4
5
6
7
8
9
SDA
A A A
Data
Data t Registero
R/W
1
0 0 0 0 0
0 1
P
S
0
1
0 0 0 0
AD
DR
0
Acknowledge
From Slave
Acknowledge
From Slave
Start Condition
Command ByteSlave Address
Acknowledge
From Slave
0 0 0 0
AD
DR
0
1
S
0
A A A
R/W
A
PNA
S
1
MS LS
Slave Address
Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master transmitter
slave transmitter.
becomes master receiver, and
slave receiver becomes
0 0 0 0
AD
DR
0
1
R/W
TCA8418
SCPS215B –SEPTEMBER 2009–REVISED MARCH 2010 www.ti.com
Figure 9. Write to Output Port Register
Figure 10. Write to Configuration or Polarity Inversion Register
Reads
The bus master first must send the TCA8418 address with the LSB set to a logic 0. The command byte is sent
after the address and determines which register is accessed. After a restart, the device address is sent again
but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the
TCA8418 (see Figure 11 and Figure 12). Data is clocked into the register on the rising edge of the ACK clock
pulse.
Figure 11. Read From Register
22 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TCA8418