Datasheet

0 0 0 0
AD
DR
0
1
S
0
A A A
R/W
A
PNA
S
1
MS LS
Slave Address
Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master transmitter
slave transmitter.
becomes master receiver, and
slave receiver becomes
0 0 0 0
AD
DR
0
1
R/W
1 2 3 4 5 6 7 8 9
S
0
1
0 0 0 0
AD
DR
1
A
1
A
DatafromPort
A
DatafromPort
P
SCL
SDA
INT
ReadFrom
Port
DataInto
Port
Acknowledge
FromMaster
Acknowledge
FromSlave
Acknowledge
FromMaster
t
iv
t
ir
R/W
Data1 Data4
TCA8418E
SCPS222B –MAY 2010–REVISED SEPTEMBER 2010 www.ti.com
Reads
The bus master first must send the TCA8418E address with the LSB set to a logic 0. The command byte is sent
after the address and determines which register is accessed. After a restart, the device address is sent again
but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the
TCA8418E (see Figure 11 and Figure 12). Data is clocked into the register on the rising edge of the ACK clock
pulse.
Figure 11. Read From Register
Figure 12. Read From Input Port Register
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