Datasheet

TCA8418E
SCPS222B –MAY 2010–REVISED SEPTEMBER 2010 www.ti.com
Table 4. Register Descriptions (continued)
REGISTER
ADDRESS REGISTER NAME 7 6 5 4 3 2 1 0
DESCRIPTION
N/A N/A N/A N/A N/A N/A C9IS C8IS
0×13 GPIO_INT_STAT3 GPIO interrupt status
0 0 0 0 0 0 0 0
GPIO_DAT_STAT1
0×14 GPIO data status R7DS R6DS R5DS R4DS R3DS R2DS R1DS R0DS
(read twice to clear)
GPIO_DAT_STAT2
0×15 GPIO data status C7DS C6DS C5DS C4DS C3DS C2DS C1DS C0DS
(read twice to clear)
GPIO_DAT_STAT3 N/A N/A N/A N/A N/A N/A
0×16 GPIO data status C9DS C8DS
(read twice to clear) 0 0 0 0 0 0
R7DO R6DO R5DO R4DO R3DO R2DO R1DO R0DO
0×17 GPIO_DAT_OUT1 GPIO data out
0 0 0 0 0 0 0 0
C7DO C6DO C5DO C4DO C3DO C2DO C1DO C0DO
0×18 GPIO_DAT_OUT2 GPIO data out
0 0 0 0 0 0 0 0
N/A N/A N/A N/A N/A N/A C9DO C8DO
0×19 GPIO_DAT_OUT3 GPIO data out
0 0 0 0 0 0 0 0
R7IE R6IE R5IE R4IE R3IE R2IE R1IE R0IE
0×1A GPIO_INT_EN1 GPIO interrupt enable
0 0 0 0 0 0 0 0
C7IE C6IE C5IE C4IE C3IE C2IE C1IE C0IE
0×1B GPIO_INT_EN2 GPIO interrupt enable
0 0 0 0 0 0 0 0
N/A N/A N/A N/A N/A N/A C9IE C8IE
0×1C GPIO_INT_EN3 GPIO interrupt enable
0 0 0 0 0 0 0 0
Keypad or GPIO
selection
ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
0×1D KP_GPIO1
0: GPIO 0 0 0 0 0 0 0 0
1: KP matrix
Keypad or GPIO
selection
COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
0×1E KP_GPIO2
0: GPIO 0 0 0 0 0 0 0 0
1: KP matrix
Keypad or GPIO
selection
N/A N/A N/A N/A N/A N/A COL9 COL8
0×1F KP_GPIO3
0: GPIO 0 0 0 0 0 0 0 0
1: KP matrix
ROW7 ROW6 ROW5 ROW4 ROW3 ROW2 ROW1 ROW0
0×20 GPI_EM1 GPI event mode 1
0 0 0 0 0 0 0 0
COL7 COL6 COL5 COL4 COL3 COL2 COL1 COL0
0×21 GPI_EM2 GPI event mode 2
0 0 0 0 0 0 0 0
N/A N/A N/A N/A N/A N/A COL9 COL8
0×22 GPI_EM3 GPI event mode 3
0 0 0 0 0 0 0 0
GPIO data direction
R7DD R6DD R5DD R4DD R3DD R2DD R1DD R0DD
0×23 GPIO_DIR1 0: input
0 0 0 0 0 0 0 0
1: output
GPIO data direction
C7DD C6DD C5DD C4DD C3DD C2DD C1DD C0DD
0×24 GPIO_DIR2 0: input
0 0 0 0 0 0 0 0
1: output
GPIO data direction
N/A N/A N/A N/A N/A N/A C9DD C8DD
0×25 GPIO_DIR3 0: input
0 0 0 0 0 0 0 0
1: output
GPIO edge/level detect
R7IL R6IL R5IL R4IL R3IL R2IL R1IL R0IL
0×26 GPIO_INT_LVL 1 0: low
0 0 0 0 0 0 0 0
1: high
GPIO edge/level detect
C7IL C6IL C5IL C4IL C3IL C2IL C1IL C0IL
0×27 GPIO_INT_LVL 2 0: low
0 0 0 0 0 0 0 0
1: high
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