Datasheet

TCA7408
www.ti.com SCPS235B –NOVEMBER 2011–REVISED MARCH 2013
Register 0Fh – Input Status Register
The Input Status Register reflects the incoming logic levels of the GPIOs set as inputs.
• The default value, X, is determined by the externally applied logic level.
• It only acts on read operation. Attempted writes to this register have no effect.
• For GPIOs set as outputs this register will read HIGH.
BIT B7 B6 B5 B4 B3 B2 B1 B0
DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
DEFAULT X X X X X X X X
Register 11h – Interrupt Mask Register
The Interrupt Mask Register controls the generation of an interrupt to the INT pin when the GPIO-port input state
changes state.
• When a bit in this register is set to 0, an interrupt generated by the interrupt status register causes the INT pin
to be asserted LOW.
• When a bit in this register is set to 1, the interrupt for the corresponding GPIO is disabled. The corresponding
bit in the Interrupt Status Register (13h) will still be asserted.
• INT is not affected when GPIO-port is defined as outputs.
BIT B7 B6 B5 B4 B3 B2 B1 B0
DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
DEFAULT 0 0 0 0 0 0 0 0
Register 13h – Interrupt Status Register
The Interrupt Status Register bit is asserted when the bit changes to a value opposite to the default value defined
in the Input Default State Register (09h).
• This bit is cleared and the INT pin is de-asserted upon read of this register.
• The input must be asserted back to the default state before this bit is set again.
• If the GPIO-port pin is defined as an output, this bit is never set.
• Attempted writes to this register, have no effect.
BIT B7 B6 B5 B4 B3 B2 B1 B0
DESCRIPTION GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
DEFAULT 0 0 0 0 0 0 0 0
POWER-ON RESET
When power (from 0V) is applied to V
CCP
, an internal power-on reset holds the TCA7408 in a reset condition until
V
CCP
has reached V
POR
. At that time, the reset condition is released, and the TCA7408 registers and I
2
C/SMBus
state machine initialize to their default states. After that, V
CCP
must be lowered to below V
PORF
and back up to the
operating voltage for a power-reset cycle.
• During power up, if V
CCI
ramps before V
CCP
, a power on reset event occurs and the I
2
C registers are reset.
• If V
CCP
ramps up before V
CCI
, then the device with reset as if RESET = 0
• The device is reset regardless of which V
CCx
ramps first.
RESET (RESET) INPUT
The RESET input can be asserted to initialize the system while keeping V
CCP
at its operating level. A reset can
be accomplished by holding the RESET pin low for a minimum of t
W
. The TCA7408 registers and I
2
C/SMBus
state machine are changed to their default state once RESET is low (0). Only when RESET is high (1), GPIO
registers can be accessed by the I
2
C pin. This input requires a pull-up resistor to V
CCI
, if no active connection is
used.
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