Datasheet

Data From
Shift Reg.
Write PD/PU
PDZ / PU
Register
D Q
OFF
QZ
PD/PU Data
PULL ENAB
Register
Data From
Shift Reg.
Write PULL ENAB
D Q
OFF
QZ
PULL ENAB Data
Data From
Shift Reg.
Write OUT STATE
OUT STATE
Register
OUT STATE Data
D Q
OFF
QZ
Write OUT HIGHZ
Data From
Shift Reg.
OUT HIGHZ Data
D Q
OFF
QZ
OUT HIGHZ
Register
IO DIR.
Register
Data From
Shift Reg.
IO DIR Data
Write IO DIRECTION
D Q
OFF
QZ
IN DEFAULT
Register
Data From
Shift Reg.
Write INPUT DEFAULT
D Q
OFF
QZ
INPUT DEF STATE Data
INPUT STATUS Data
D Q
OFF
QZ
Data From
Shift Reg.
Write INT MASK
INT MASK
Register
INT STAT
Register
D Q
OFF
QZ
INTERUPT STATUS Data
VDD
Q1
Q3
D1
ESD
Protection
Diode
R1
100k
GPIO
100k
R2
Q4
D2
ESD
Protection
Diode
GND
Q2
INT MASK Data
To INTz
(One of ANDed 8)
TCA7408
SCPS235B –NOVEMBER 2011–REVISED MARCH 2013 www.ti.com
SIMPLIFIED LOGIC DIAGRAM (POSITIVE LOGIC)
On power up or reset, all registers return to default values.
I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input.
If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the Output Port Register. In
this case, there are low impedance paths between the I/O pin and either V
CCP
or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
Q4 is turned on at power-on to enable the pull down resistor. Q3 and Q4 are enabled accordingly to the Pull-up/-
down Select Register and the Pull-up/-down Enable Register.
When the GPIO-port is set as an output the input buffers are disabled such that the bus is allowed to float.
I
2
C INTERFACE
The bidirectional I
2
C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to V
CCI
through a pull-up resistor when connected to the output stages of a device. Data transfer may
be initiated only when the bus is not busy.
I
2
C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output, while the SCL input is high. After the Start condition, the device address byte is sent, most
significant bit (MSB) first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an acknowledge (ACK), a low on the SDA
input/output during the high of the ACK-related clock pulse. The address (ADDR) input of the slave device must
not be changed between the Start and the Stop conditions.
On the I
2
C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop).
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