Datasheet
TCA7408
www.ti.com
SCPS235B –NOVEMBER 2011–REVISED MARCH 2013
APPLICATION INFORMATION
POWER-ON RESET REQUIREMENTS
In the event of a glitch or data corruption, TCA7408 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in the figures below:
Figure 12. V
CC
is Lowered Below 0.2 V or 0 V and Then Ramped Up to V
CC
Figure 13. V
CC
is Lowered Below the POR Threshold, Then Ramped Back Up to V
CC
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (t
GW
)
and height (t
GH
) are dependent on each other. The bypass capacitance, source impedance, and device
impedance are factors that affect power-on reset performance. Figure 14 provides more information on how to
measure these specifications.
Figure 14. Glitch Width and Glitch Height
V
POR
is critical to the power-on reset. V
POR
is the voltage level at which the reset condition is released and all the
registers and the I2C/SMBus state machine are initialized to their default states. The value of V
POR
differs based
on the V
CC
being lowered to or from 0. Figure 15 provides more details on this specification.
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