Datasheet

S
1 2 8 9
NACK
ACK
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
Start
Condition
ClockPulsefor
Acknowledgment
0
Slave Address
1
0 0
0 1
AD
DR
R/W
Fixed
Programmable
TCA6424
SCPS175A –NOVEMBER 2007–REVISED NOVEMBER 2009 www.ti.com
Figure 3. Acknowledgment on the I
2
C Bus
Table 3. Interface Definition
BIT
BYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H L L L H ADDR R/W
P07 P06 P05 P04 P03 P02 P01 P00
I/O data bus P17 P16 P15 P14 P13 P12 P11 P10
P27 P26 P25 P24 P23 P22 P21 P20
Device Address
The address of the TCA6424 is shown in Figure 4.
Figure 4. TCA6424 Address
Table 4. Address Reference
ADDR I
2
C BUS SLAVE ADDRESS
L 34 (decimal), 22 (hexadecimal)
H 35 (decimal), 23 (hexadecimal)
The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read
operation, while a low (0) selects a write operation.
Control Register and Command Byte
Following the successful acknowledgment of the address byte, the bus master sends a command byte, which is
stored in the control register in the TCA6424. Four bits of this data byte state the operation (read or write) and
the internal registers (input, output, polarity inversion, or configuration) that will be affected. The control register
can be written or read through the I
2
C bus. The command byte is sent only during a write transmission.
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