Datasheet

29
I/O Port
Shift
Register
24 Bits
Input
Filter
30
Power-On
Reset
Read Pulse
Write Pulse
26
27
25
GND
V
CCP
SDA
SCL
ADDR
I C Bus
Control
2
RESET
28
INT
Interrupt
Logic
LP Filter
32
V
CCI
31
P27
P17–P10
P07–P00
–P20
Data From
Shift Register
Write Configuration
Pulse
Write Pulse
Read Pulse
Write Polarity Pulse
Polarity
Inversion
Register
Input
Port
Register
Output
Port
Register
Configuration
Register
V
CCP
GND
Input Port
Register Data
Polarity
Register Data
ESD Protection Diode
P00 to P27
Output Port
Register Data
To INT
Q1
Q2
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
D
FF
C
K
Q
Q
Data From
Shift Register
Data From
Shift Register
TCA6424
SCPS175A –NOVEMBER 2007–REVISED NOVEMBER 2009 www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
A. All I/Os are set to inputs at reset.
B. Pin numbers shown are for the RGJ package.
Simplified Schematic of P00 to P27
A. On power up or reset, all registers return to default values.
4 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated
Product Folder Link(s): TCA6424