Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION/ORDERING INFORMATION
- DESCRIPTION/ORDERING INFORMATION (CONTINUED)
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- I2C INTERFACE TIMING REQUIREMENTS
- RESET TIMING REQUIREMENTS
- SWITCHING CHARACTERISTICS
- TYPICAL CHARACTERISTICS
- PARAMETER MEASUREMENT INFORMATION
- APPLICATION INFORMATION
- REVISION HISTORY
B2 B1
B0B5
B4
B3
AI
B6
TCA6424A
SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
www.ti.com
The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command
byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set
to logic 0.
If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to
program and/or read the 3 register banks sequentially. If more than 3 bytes of data are written when AI is 1,
previous data in the selected registers will be overwritten. Reserved registers are skipped and not accessed
(refer to Table 5).
If AI is 0, the 2 least significant bits are not incremented after data is read or written. During a read operation, the
same register bank is read each time. During a write operation, data is written to the same register bank each
time.
Reserved command codes and command byte outside the range stated in the Command Byte table must not be
accessed for proper device functionality.
Figure 5. Control Register Bits
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