Datasheet

0 0 0 1
AD
DR
0
1
S
0
A A A
R/W
A
PNA
S
1
MSB LSB
MSB LSB
Slave Address
Acknowledge
FromSlave
CommandByte
DataFromUpper
orLowerByte
ofRegister
LastByte
Data
Acknowledge
FromSlave
Acknowledge
FromSlave
Slave Address
DataFromLower
orUpperByte
ofRegister
FirstByte
Data
No Acknowledge
FromMaster
Acknowledge
FromMaster
Atthismoment,mastertransmitter
slavetransmitter.
becomesmasterreceiver,and
slavereceiverbecomes
0 0 0 1
AD
DR
0
1
R/W
1 2 3 4 5 6 7 8 9
S
0
1
0 0 0 1
AD
DR
1
A
Data 1 Data 2
Data 3 Data 4
A
I0.x
A
I1.x
A
I2.x
1
I0.x
P
SCL
SDA
INT
Read From
Port 0
Data Into
Port 0
Read From
Port 1
Data Into
Port 1
Read From
Port 2
Data Into
Port 2
Acknowledge
From Master
Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
t
iv
t
ir
R/W
TCA6424A
www.ti.com SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Figure 8. Read From Register
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A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from P port (see Figure 8).
C. Auto-increment mode is enabled.
Figure 9. Read Input Port Register
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