Datasheet

TCA6424A
www.ti.com SCPS193B –JULY 2010–REVISED SEPTEMBER 2010
Power-On Reset
When power (from 0 V) is applied to V
CCP
, an internal power-on reset holds the TCA6424A in a reset condition
until V
CCP
has reached V
POR
. At that time, the reset condition is released, and the TCA6424A registers and
I
2
C/SMBus state machine initializes to their default states. After that, V
CCP
must be lowered to below 0.2 V and
back up to the operating voltage for a power-reset cycle.
ADD TABLE WITH SPECS AND DEFINITIONS TO SUPPORT POR OPERATION
Reset Input (RESET)
The RESET input can be asserted to initialize the system while keeping the V
CCP
at its operating level. A reset
can be accomplished by holding the RESET pin low for a minimum of t
W
. The TCA6424A registers and
I
2
C/SMBus state machine are changed to their default state once RESET is low (0). When RESET is high (1),
the I/O levels at the P port can be changed externally or through the master. This input requires a pullup resistor
to V
CCI
, if no active connection is used.
Interrupt Output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time t
iv
, the signal
INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or
when data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL signal. Interrupts that occur
during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt during this
pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur, if the
state of the pin does not match the contents of the Input Port register.
The INT output has an open-drain structure and requires pullup resistor to V
CCP
or V
CCI
depending on the
application. If the INT signal is connected back to the processor that provides the SCL signal to the TCA6424A
then the INT pin has to be connected to V
CCI
. If not, the INT pin can be connected to V
CCP
.
Bus Transactions
Data is exchanged between the master and TCA6424A through write and read commands.
Writes
Data is transmitted to the TCA6424A by sending the device address and setting the least-significant bit (LSB) to
a logic 0 (see Figure 4 for device address). The command byte is sent after the address and determines which
register receives the data that follows the command byte. There is no limitation on the number of data bytes sent
in one write transmission.
The twelve registers within the TCA6424A are grouped into four different sets. The four sets of registers are input
ports, output ports, polarity inversion ports and configuration ports. After sending data to one register, the next
data byte is sent to the next register in the group of 3 registers (see Figure 6 and Figure 7). For example, if the
first byte is send to Output Port 2 (register 6), the next byte is stored in Output Port 0 (register 4).
There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register
may be updated independently of the other registers.
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