Datasheet

0 0 0 0
AD
DR
0
1
S
0
A A A
R/W
A
PNA
S
1
MSB LSB
MSB LSB
Slave Address
Acknowledge
From Slave
Command Byte
Data From Upper
or Lower Byte
of Register
Last Byte
Data
Acknowledge
From Slave
Acknowledge
From Slave
Slave Address
Data From Lower
or Upper Byte
of Register
First Byte
Data
No Acknowledge
From Master
Acknowledge
From Master
At this moment, master transmitter
slave transmitter.
becomes master receiver, and
slave receiver becomes
0 0 0 0
AD
DR
0
1
R/W
1 2
SCL
3
4
5
6
7
8
SDA A A A
Data0
Datat Registero
R/W
9
0/10 0 0 0 0
1
1/0
MSB LSB
Data1
MSB LSB
AS
0
1
0 0 0 0
AD
DR
0
1 2
3
4
5
6
7
8 9
1 2
3
4
5
6
7
8 9
1 2
3
4
5
P
Acknowledge
FromSlave
Acknowledge
FromSlave
StartCondition
CommandByteSlave Address
Acknowledge
FromSlave
Datat Registero
TCA6416A
SCPS194A –MAY 2009–REVISED NOVEMBER 2009 www.ti.com
Figure 9. Write to Configuration or Polarity Inversion Registers
Reads
The bus master first must send the TCA6416A address with the LSB set to a logic 0 (see Figure 6 for device
address). The command byte is sent after the address and determines which register is accessed.
After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register
defined by the command byte then is sent by the TCA6416A (see Figure 10 and Figure 11).
After a restart, the value of the register defined by the command byte matches the register being accessed when
the restart occurred. For example, if the command byte references Input Port 1 before the restart, and the restart
occurs when Input Port 0 is being read, the stored command byte changes to reference Input Port 0. The original
command byte is forgotten. If a subsequent restart occurs, Input Port 0 is read first. Data is clocked into the
register on the rising edge of the ACK clock pulse. After the first byte is read, additional bytes may be read, but
the data now reflects the information in the other register in the pair. For example, if Input Port 1 is read, the next
byte read is Input Port 0.
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
Figure 10. Read From Register
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