Datasheet

SDA
SCL
S P
StartCondition
StopCondition
SDA
SCL
DataLine
Change
S
1 2 8 9
NACK
ACK
DataOutput
byTransmitter
DataOutput
byReceiver
SCL From
Master
Start
Condition
ClockPulsefor
Acknowledgment
TCA6408A
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AStopcondition,alow-to-hightransitionontheSDAinput/outputwhiletheSCLinputishigh,issentbythe
master(seeFigure1).
AnynumberofdatabytescanbetransferredfromthetransmittertoreceiverbetweentheStartandtheStop
conditions.EachbyteofeightbitsisfollowedbyoneACKbit.ThetransmittermustreleasetheSDAlinebefore
thereceivercansendanACKbit.ThedevicethatacknowledgesmustpulldowntheSDAlineduringtheACK
clockpulse,sothattheSDAlineisstablelowduringthehighpulseoftheACK-relatedclockperiod(see
Figure3).Whenaslavereceiverisaddressed,itmustgenerateanACKaftereachbyteisreceived.Similarly,
themastermustgenerateanACKaftereachbytethatitreceivesfromtheslavetransmitter.Setupandhold
timesmustbemettoensureproperoperation.
Amasterreceiversignalsanendofdatatotheslavetransmitterbynotgeneratinganacknowledge(NACK)after
thelastbytehasbeenclockedoutoftheslave.ThisisdonebythemasterreceiverbyholdingtheSDAlinehigh.
Inthisevent,thetransmittermustreleasethedatalinetoenablethemastertogenerateaStopcondition.
Figure1.DefinitionofStartandStopConditions
Figure2.BitTransfer
Figure3.AcknowledgmentonI
2
CBus
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