Datasheet

Reads
00
1
S
00 0
AD
DR
0
A A
Data from Register
Slave Address
Slave Address
R/W
ACK From
Slave
Command Byte
S
00
1
00 0
R/W
1
A
Data
A
Data
Data from Register
NA
P
Last Byte
At this moment, master-transmitter
becomes master-receiver, and
slave-receiver becomes
slave-transmitter
ACK From
Slave
ACK From
Slave
ACK From
Master
NACK From
Master
First byte
AD
DR
SCL
SDA
INT
Start
Condition
R/W
ReadFrom
Port
DataInto
Port
Stop
Condition
ACKFrom
Master
NACKFrom
Master
ACKFrom
Slave
DataFromPort
Slave Address DataFromPort
1 9
R
765432
00
1
S
00
0
AD
DR
1
A
Data1 Data4
A NA P
Data2 Data3 Data4
Data5
INT iscleared
byReadfromPort
Stopnotneeded
toclear INT
t
ph
t
ps
t
ir
t
iv
TCA6408A
www.ti.com .............................................................................................................................................................SCPS192C–APRIL2009–REVISEDJULY2009
ThebusmasterfirstmustsendtheTCA6408AaddresswiththeLSBsettoalogic0(seeFigure4fordevice
address).Thecommandbyteissentaftertheaddressanddetermineswhichregisterisaccessed.
Afterarestart,thedeviceaddressissentagainbut,thistime,theLSBissettoalogic1.Datafromtheregister
definedbythecommandbytethenissentbytheTCA6408A(seeFigure8andFigure9).
DataisclockedintotheregisterontherisingedgeoftheACKclockpulse.
Figure8.ReadFromRegister
<br/>
A.TransferofdatacanbestoppedatanytimebyaStopcondition.Whenthisoccurs,datapresentatthelatest
acknowledgephaseisvalid(outputmode).Itisassumedthatthecommandbytepreviouslyhasbeensetto00(read
InputPortRegister).
B.Thisfigureeliminatesthecommandbytetransfer,arestart,andslaveaddresscallbetweentheinitialslaveaddress
callandactualdatatransferfromPport(seeFigure8).
Figure9.ReadFromInputPortRegister
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