Datasheet

54.0 54.2
0.0
1.0
2.5
–0.5
0.5
1.5
3.0
2.0
3.5
54.4 54.6 54.8
t (s)
(V)
55.0 55.2 55.4 55.6 55.8 56.0
VXSDAOUT
VXSDAIN
52.0
52.025
0.0
1.0
2.5
–0.5
0.5
1.5
3.0
2.0
3.5
52.075 52.1 52.125
t (s)
(V)
52.15 52.175
VXSDAIN
Delay: 72.258
VXSDAOUT
TCA4311A
www.ti.com SCPS226A –JANUARY 2011–REVISED JULY 2012
10-kΩ pullup resistors and 100 pF equivalent capacitance on both sides of the part. By comparison with Figure 2,
the V
CC
= 3.3 V curve shows that increasing the capacitance from 50 pF to 100 pF results in a t
PHL
increase from
55 ns to 75 ns. Larger output capacitances translate to longer delays (up to 150 ns). Users must quantify the
difference in propagation times for a rising edge versus a falling edge in their systems and adjust setup and hold
times accordingly.
Figure 1. Input-Output Connection t
PLH
Figure 2. Input-Output Connection t
PHL
Rise-Time Accelerators
Once connection has been established, rise-time accelerator circuits on all four SDA and SCL pins are activated.
These allow the user to choose weaker DC pullup currents on the bus, reducing power consumption while still
meeting system rise-time requirements. During positive bus transitions, the TCA4311A switches in 2 mA (typical)
of current to quickly slew the SDA and SCL lines once their DC voltages exceed 0.6 V. Using a general rule of
20 pF of capacitance for every device on the bus (10 pF for the device and 10 pF for interconnect), choose a
pullup current so that the bus will rise on its own at a rate of at least 1.25 V/μs to guarantee activation of the
accelerators.
For example, assume an SMBus system with V
CC
= 3 V, a 10-kΩ pullup resistor and equivalent bus capacitance
of 200 pF. The rise-time of an SMBus system is calculated from (V
IL(MAX)
– 0.15 V) to (V
IH(MIN)
+ 0.15 V), or 0.65
V to 2.25 V. It takes an RC circuit 0.92 time constants to traverse this voltage for a 3 V supply; in this case, 0.92
× (10 kΩ × 200 pF) = 1.84 μs. Thus, the system exceeds the maximum allowed rise-time of 1 μs by 84%.
However, using the rise-time accelerators, which are activated at a DC threshold of below 0.65 V, the worst-case
rise-time is: (2.25 V – 0.65 V) × 200 pF/1 mA = 320 ns, which meets the 1 μs rise-time requirement.
READY Digital Output
This pin provides a digital flag which is low when either EN is low or the start-up sequence described earlier in
this section has not been completed. READY goes high when EN is high and start-up is complete. The pin is
driven by an open drain pull-down capable of sinking 3 mA while holding 0.4 V on the pin. Connect a resistor of
10 kΩ to V
CC
to provide the pullup.
EN Low Current Disable
Grounding the EN pin disconnects the backplane side from the card side, disables the rise-time accelerators,
drives READY low, disables the bus precharge circuitry and puts the part in a near-zero current state. When the
pin voltage is driven all the way to V
CC
, the part waits for data transactions on both the backplane and card sides
to be complete (as described in the Start-Up section) before reconnecting the two sides.
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